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1 green hybrid digital four phase pwm controller for intel vr12.5? cpus ISL95820 the ISL95820 pulse width modula tion (pwm) controller ic provides a complete low-cost solution for intel vr12.5? compliant microprocessor core po wer supplies. it provides the control and protection for a vo ltage regulator (vr). the vr incorporates 3 integrated drivers and can operate in 4-, 3-, 2- or 1-phase configurations. the vr uses a serial control bus to communicate with the cpu and ac hieve lower cost and smaller board area. the vr utilizes intersil?s robust ripple regulator r3 technology?. the r3? modulator has many advantages compared to traditional modulators, including faster transient response, variable switching fr equency in response to load transients, and improved light load efficiency due to diode emulation mode with load-dependent low switching frequency. the ISL95820 has several other key features. it supports either dcr current sensing with a single ntc thermistor for dcr temperature compensation, or more precise resistor current sensing if desired. the output comes with remote voltage sense, programmable v boot voltage, i max, voltage transition slew rate and swit ching frequency, adjustable overcurrent protection and power-good signal. features ?serial data bus ? smbus/pmbus/i 2 c interface with svid conflict free ? configurable 4-, 3-, 2- or 1-phase for the output using three integrated gate drivers ? green hybrid digital r3? modulator - excellent transient response - phase shedding with power state selection - diode emulation in single-phase for high light-load efficiency ? 0.5% system accuracy over-temperature ? supports multiple current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? differential remote voltage sensing ?programmable v boot voltage at start-up ? resistor programmable i max , load line, diode emulation, slope compensation, and switching frequency ? adaptive body diode conduction time reduction applications ? intel vr12.5 desktop computers intersil driver ISL95820 v in v in v core v in v in phase4 phase3 phase2 phase1 figure 1. simplified application circuit caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) and r3 technology are trademarks ow ned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. february 4, 2013 fn8318.0
ISL95820 2 fn8318.0 february 4, 2013 table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 multiphase power conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 multiphase r3? modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 diode emulation and period stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 adaptive body diode conduction time reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 programming resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 general design guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 integrated driver operation and adaptive shoot-through protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output filter design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 inductor current sensing and balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 current sense circuit adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 vr_hot#/alert# behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 serial vid (svid) supported data and configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 serial pmbus (i2c/smbus/pmbus) supported da ta and configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ISL95820 3 fn8318.0 february 4, 2013 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL95820crtz isl9582 0crtz 0 to +70 40 ld 5x5 tqfn l40.5x5 ISL95820irtz isl9582 0irtz -40 to +85 40 ld 5x5 tqfn l40.5x5 ISL95820eval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL95820 . for more information on msl please see techbrief tb363 . pin configuration ISL95820 (40 ld tqfn) top view gnd pad (bottom) 40 39 38 37 36 35 34 33 32 31 29 30 27 28 25 26 23 24 21 22 11 12 13 14 15 16 17 18 19 20 2 1 4 3 6 5 8 7 10 9 vr_hot# ntc comp fb fb2 fb3 isen4 isen2 isen1 rtn isumn isump vdd boot1 ugate3 lgate3 ugate2 phase2 sda i2clk i2data prog1 prog2 phase1 phase3 vccp boot3 imon boot2 lgate1 prog3 alert# sclk isen3 vin pgood vr_on ugate1 pwm4 lgate2
ISL95820 4 fn8318.0 february 4, 2013 pin descriptions pin # symbol description bottom pad gnd signal common of the ic. unless otherwise stated, signals are referenced to the gnd pad. it should also be used as the thermal pad for heat removal. 1 vr_on controller enable input. a high level logic signal on this pin enables the controller. 2 pgood power-good open-drain output indicati ng when vr is able to supply regulated voltage. pull-up externally to vdd or to a lower supply, such as 3.3v. 3 imon vr output current monitor. imon sources a current proporti onal to the regulator output current. a resistor to ground determines the scaling of the imon voltage to output current. 4 vr_hot# open drain thermal overload output indica tor. part of the communication bus with the cpu. 5 ntc the thermistor input to vr_hot# circ uit. use it to monitor vr temperature. 6 comp this pin is the output of the vr error amplifier. it pr ovides error amplifier feedback to the compensation network. 7 fb this pin is the inverting input of the vr error amplifier. a dac-derived voltage equal to the vid reference voltage is connected internally to the non-inverting error amplifier input. 8 fb2 there is an internal switch between fb pin and fb2 pin. the switch is off (open) when vr is in 1-phase mode and is on (closed) otherwise. the components connecting to fb2 are used to adjust the compensation in 1-phase mode to achieve optimum performance for vr. 9 fb3 there is an internal switch between pins fb and fb3. the switch will be on (closed) in droop mode (whenever programmable output dc loadline operation is enabled), and of f (open) when no-droop mode is selected. the purpose is to include a resistor in parallel with the fixed droop resistor when droop is active, and to isolate that resistor when droop is inactive. this parallel resistor increases the open-loop ga in of the compensator while droop is active. the effective droop (output dc loadline) programming resistance is the parallel combination of these two resistors. 10 isen4 individual current sensing for phase4. when isen4 is pulle d to vdd (5v), the controller will disable vr phase 4. this signal is used to monitor for and to correct phase current imbalance. 11 isen3 individual current sensing for phase3. when isen4 and isen 3 is pulled to vdd (5v), the controller will disable vr phases 4 and 3. do not disable phase 3 without also disabling phase 4. this signal is used to monitor for and to correct phase current imbalance. 12 isen2 individual current sensing for phase 2. when isen4, isen 3 and isen2 are pulled to vdd (5v), the controller will disable vr phases 4, 3 and 2. do not disable ph ase 2 without also di sabling phases 3 and 4. this si gnal is used to monitor for and to correct phase current imbalance. 13 isen1 individual current sensing for phase 1. this signal is used to monitor for and to correct phase current imbalance. 14 rtn remote ground (return) voltage sensing. part of the differential remote vr voltage sense network. 15, 16 isumn and isump vr droop current sensing inputs. 17 vdd +5v bias power. 18 boot1 phase 1 internal gate driver high-side mosfet bootstra p capacitor connection. connect an mlcc capacitor between the boot1 and the phase1 pins. the boot capacitor is charged th rough an internal boot diode connected from the vccp pin to the boot1 pin each time the phase1 pin drops below vccp minus the voltage dropped across the internal boot diode. 19 phase1 current return path for phase 1 hi gh-side mosfet gate driver. connect the phase1 pin to the node consisting of the high-side mosfet source, the lo w-side mosfet drain, and the output inductor of phase1. 20 ugate1 output of phase 1 high-side mosfet gate driver. conn ect the ugate1 pin to the gate of phase 1 high-side mosfet. 21 lgate1 output of phase 1 low-side mosfet gate driver. conn ect the lgate1 pin to the gate of phase 1 low-side mosfet. 22 boot2 phase 2 internal gate driver high-side mosfet bootstra p capacitor connection. connect an mlcc capacitor between the boot2 and the phase2 pins. the boot capacitor is charged th rough an internal boot diode connected from the vccp pin to the boot2 pin, each time the phase2 pin drops below vccp minus the voltage dropped across the internal boot diode. 23 phase2 current return path for phase 2 hi gh-side mosfet gate driver. connect the phase2 pin to the node consisting of the high-side mosfet source, the lo w-side mosfet drain, and the output inductor of phase 2. 24 ugate2 output of phase 2 high-side mosfet gate driver. conn ect the ugate2 pin to the gate of phase 2 high-side mosfet. 25 vccp input voltage bias for the internal gate drivers. connect +5v or +12v to the vccp pin. decouple with at least 1f of an mlcc capacitor. diode emulation mode must be disabled (using prog2 pin resistor) for +5v driver operation.
ISL95820 5 fn8318.0 february 4, 2013 26 lgate2 output of phase 2 low-side mosfet gate driver. connect the lgate2 pin to the gate of phase 2 low-side mosfet. 27 lgate3 output of phase 3 low-side mosfet gate driver. connect the lgate3 pin to the gate of phase 3 low-side mosfet. 28 phase3 current return path for phase 3 high-side mosfet gate driver. connect the phase3 pin to the node consisting of the high-side mosfet source, the low-side mosfet drain, and the output inductor of phase 3. 29 ugate3 output of phase 3 high -side mosfet gate driver. connect the ugate3 pin to the gate of phase 3 high-side mosfet. 30 boot3 phase 3 internal gate driver high -side mosfet bootstrap capacitor connecti on. connect an mlcc capacitor between the boot3 and the phase3 pins. the boot capacitor is charged through an internal boot diode connected from the vccp pin to the boot3 pin, each time the phase3 pin drops below vccp minus the voltage dropped across the internal boot diode. 31 pwm4 pwm output for phase 4. phase 4 requires an external ga te driver device. the intersil isl6625a driver is recommended. 32 vin input supply voltage, used for feed-forward. connect this pin to the input voltage of the output drive stages. 33 prog3 a resistor from the prog3 pin to gnd programs the internal modulator slope compensation and switching frequency. 34 prog2 a resistor from the prog2 pin to gnd programs the initial power-up voltage (v boot ), enables/disables the dc loadline (droop) function, and enables/disables diode emulation mode (dem) in power states 2 and 3 (ps2 and ps3). 35 prog1 a resistor from prog1 pin to gnd programs i max , the designed nominal maximum load current of the vr. the value of i max establishes the scaling of the reported vr output current , which can be read via the svid or pmbus interfaces. the prog1 resistor is chosen such that the reported i max current is ffh when the output current is equal to the maximum load current. 36, 37 i2data, i2clk interface of smbus/pmbus/i 2 c. tie to vcc with 4.7k pull-up resistor when not used. 38, 39, 40 sda, alert#, sclk, svid communication bus between the cpu and the vr. pin descriptions (continued) pin # symbol description
ISL95820 6 fn8318.0 february 4, 2013 block diagram rtn e/a fb idroop current sense isump isumn comp ov fault pgood _ + _ + + + ibal fault oc fault isen1 isen2 isen3 current balancing digital interface sda alert# sclk dac temp monitor ntc vr_hot# t_monitor imax vboot droop frequency slope comp prog vr_on mode d/a a/d idroop r3 tm modulator /driver control vdd gnd prog1 prog2 vin imon prog3 fb2 isen4 fb2/fb3 circuit fb3 i2data i2clk driver driver lgate1 phase1 ugate1 boot1 driver driver lgate2 phase2 ugate2 boot2 pwm4 driver driver lgate3 phase3 ugate3 boot3 vccp
ISL95820 7 fn8318.0 february 4, 2013 typical application circuit gnd ISL95820 l2 l1 isen3 rsum2 rsum1 rn cn ri l3 rsum3 12v isen2 isump isumn risen2 risen1 risen3 isen1 vsumn cisen3 cisen2 cisen1 cvsumn vcore vdd rdroop vr_on pgood vsssense vccsense rntc c fb2 vr_on comp rtn pgood ntc sda sda alert# alert# sclk sclk vr_hot# vr_hot# prog2 rrog3 +5v imon vin 10 10 10 l4 10 rsum4 risen4 isen4 prog1 cisen4 fb phase2 ugate2 boot2 vccp lgate2 phase1 ugate1 boot1 lgate1 pwm4 vcc ugate lgate phase boot pwm lvcc gnd isl6625a phase3 ugate3 boot3 lgate3 fb3 i2clk smbus/pmbus/i2c data i2data smbus/pmbus/i2c clock vccp 12v figure 2. typical ISL95820 application circuit using inductor dcr sensing
ISL95820 8 fn8318.0 february 4, 2013 absolute maximum rating s thermal information vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v vccp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15v boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +36v ugate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v dc to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v dc to v vccp + 0.3v gnd - 5v (<100ns pulse width, 2j) to v vccp + 0.3v phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v dc to 25v dc gnd - 8v (<400ns, 20j) to 30v (<200ns, v boot - gnd < 36v) open drain outputs, pgood, vr_hot#, alert#. . . . . . . . . . -0.3v to +7v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vdd + 0.3v thermal resistance (typical) ja (c/w) jc (c/w) 40 ld tqfn package (notes 4, 5) . . . . . . . 31 3 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . -65c to +150c maximum junction temperature (plastic package) . . . . . . . . . . . +150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . -65c to +150c recommended operating conditions supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% input voltage, vin (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.5v to 20.0v driver supply voltage, vccp (note 6). . . . . . . . . . . . . . . . . +4.5v to +13.2v ambient temperature crtz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c irtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c junction temperature crtz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +125c irtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. it is recommended that vin+vccp not exceed 24v no minally. for vccp < 7v, diode emulation mode (dem) must be disabled using the prog2 pin programming resistor. electrical specifications operating conditions: v dd = 5v, t a = 0c to +70c (ISL95820crtz), t a = -40c to +85c (ISL95820irtz), f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature ranges. parameter symbol test conditions min (note 7) typ max (note 7) units input power supplies vdd supply current i vdd v vdd = 5v; vr_on = 1v 6.4 8.0 ma v vdd = 5v; vr_on = 0v 125 a vin supply current r vin v vin = 25v; vr_on = 1v 600 k ? i vin v vin = 25v; vr_on = 0v 1 a vccp no load switching supply current i vccp v vccp = 12v; f sw = f sw _300k; phases 1-3 active; c boot1,2,3 = 0.1f 8ma v vccp = 12v; phases inactive 0.72 1.5 ma power-on-reset thresholds vdd power-on-reset threshold vdd_por r v vdd rising 4.3 4.35 4.5 v vdd_por f v vdd falling 4.0 4.15 4.3 v vin power-on-reset threshold vin_por r v vin rising 3.75 4.00 4.5 v vin_por f v vin falling 3.05 3.50 3.7 v vccp power-on-reset threshold vccp_por r v vccp rising 4.0 4.30 4.5 v vccp_por f v vccp falling 3.45 3.90 4.1 v system and references maximum output voltage v out(max) vid = [10110101] 2.3 v minimum output voltage v out(min) vid = [00000001] 0.5 v fast slew rate (for vid changes) 10 12 mv/s slow slew rate (for vid changes) 2.5 3mv/s
ISL95820 9 fn8318.0 february 4, 2013 system accuracy crtz error (v out) no load; closed loop, active mode range, vid = 1.00v to 2.3v, - 0.5 +0.5 % vid = 0.80v to 0.99v - 5+5 mv vid = 0.5v to 0.79v - 8+8 mv irtz error (v out ) no load; closed loop, active mode range, vid = 1.00v to 2.3v - 0.8 +0.8 % vid = 0.8v to 0.99v - 8+8 mv vid = 0.5v to 0.79v - 10 +10 mv internal v boot crtz 1.64 1.65 1.66 v 1.69 1.70 1.71 v 1.74 1.75 1.76 v irtz 1.635 1.65 1.665 v 1.685 1.70 1.715 v 1.735 1.75 1.765 v channel frequency 200khz configuration f sw _200k 180 200 220 khz 300khz configuration f sw _300k 275 300 325 khz 450khz configuration f sw _450k 410 450 490 khz amplifiers current-sense amplifier input offset crtz i fb = 0a - 0.2 +0.2 mv irtz i fb = 0a - 0.3 +0.3 mv error amp dc gain a v0 119 db error amp gain-bandwidth product gbw c l = 20pf 17 mhz isen isen offset voltage maximum of i sen - minimum of i sen 1 mv isen input bias current 20 na gate driver bootstrap switches (phases 1-3) on-resistance r f 40 ? reverse leakage i r v vddp = 12v, v vr_on = 0, boot and phase connected and total current measured 0.2 a gate driver outputs (phases 1-3) ugate pull-up resistance r ugpu 250ma source current 3.70 ? ugate source current i ugsrc ugate - phase = 2.5v 1.30 a ugate pull-down resistance r ugpd 250ma sink current 1.41 ? ugate sink current i ugsnk ugate - phase = 2.5v 1.27 a lgate pull-up resistance r lgpu 250ma source current 2.75 ? lgate source current i lgsrc lgate - vssp = 2.5v 1.75 a lgate pull-down resistance r lgpd 250ma sink current 0.60 ? lgate sink current i lgsnk lgate - vssp = 2.5v 2.14 a electrical specifications operating conditions: v dd = 5v, t a = 0c to +70c (ISL95820crtz), t a = -40c to +85c (ISL95820irtz), f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature ranges. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units
ISL95820 10 fn8318.0 february 4, 2013 ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load, v vddp = 7v 59 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load, v vddp = 7v 37 ns pwm4 (phase 4) pwm4 output low v 0l sinking 5ma 1.0 v pwm4 output high v 0h sourcing 5ma 4.5 v pwm4 tri-state leakage pwm = 2.5v 1 a protection overvoltage threshold ov h v sen > setpoint for >1s, set_ov = 00h vid + 300mv v v sen > setpoint for >1s, set_ov = 01h 3.3 v current imbalance threshold one i sen above another isen for >3.2ms 19 mv overcurrent threshold (see table 1 for configuration and ps n dependencies.) ocp_th ps0 in 4-, 3-, 2-, 1-phase configuration, or any psx in 1-phase configuration 54 60 66 a ps1 in 3-phase configuration 36 40 44 a ps1 in 4-phase configuration ps1/2/3 in 2-phase configuration 27 30 33 a ps2/3 in 4-, 3-phase configuration 18 20 22 a ntc source current ntc = 1.3v 54 60 66 a ntc vr_hot# trip voltage, tz 7fh to tz ffh threshold ntc voltage forced, voltage falling threshold 0.881 0.893 0.905 v ntc thermal alert# trip voltage, tz 3fh to tz 7fh threshold ntc voltage forced, voltage falling threshold 0.92 0.932 0.944 v ntc vr_hot# reset voltage, tz 7fh to tz 3fh threshold ntc voltage forced, voltage rising threshold 0.923 0.936 0.948 v ntc thermal alert# reset voltage, tz 3fh to tz 1fh threshold ntc voltage forced, voltage rising threshold 0.96 0.974 0.986 v power-good and protection monitors pgood low voltage v ol i pgood = 4ma 0.15 0.4 v pgood leakage current i oh pgood = 3.3v 1 a pgood delay tpgd time from vr_on high to pgood high; v boot = 1.7v 3ms vr_hot# low resistance i vr_hot# = 10ma 7 12 ? vr_hot# leakage current v vr_hot# = 5v 1 a alert# low resistance i alert# = 10ma 7 12 ? alert# leakage current v alert = 5v 1 a logical and serial interface vr_on input low v il 0.3 v vr_on input high v ih crtz 0.7 v v ih irtz 0.75 v electrical specifications operating conditions: v dd = 5v, t a = 0c to +70c (ISL95820crtz), t a = -40c to +85c (ISL95820irtz), f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature ranges. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units
ISL95820 11 fn8318.0 february 4, 2013 vr_on leakage current i vr_on vr_on = 0v - 1 0a vr_on = 1v 3.5 6 a sclk maximum speed 42 mhz sclk minimum speed 13 mhz sclk, sda leakage vr_on = 0v, sclk and sda = 0v and 1v - 11 a vr_on = 1v, sclk and sda = 1v - 21 a vr_on = 1v, sda = 0v - 26 ? 21 ? 16 a vr_on = 1v, sclk= 0v - 52 ? 42 ? 32 a sda low resistance i sda = 10ma 7 12 ? i 2 clk maximum speed 400 khz i 2 clk minimum speed 50 khz i 2 c timeout 25 30 35 ms i 2 data low resistance i i2data = 4ma 28 40 ? i 2 clk, i 2 data leakage vr_on = 0v, i 2 clk and i 2 data = 0v and 1v - 11 a vr_on = 1v, i 2 clk and i 2 data = 1v - 21 a vr_on = 1v, i 2 data = 0v - 11 a vr_on = 1v, i 2 clk= 0v - 11 a note: 7. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications operating conditions: v dd = 5v, t a = 0c to +70c (ISL95820crtz), t a = -40c to +85c (ISL95820irtz), f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature ranges. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units
ISL95820 12 fn8318.0 february 4, 2013 theory of operation the ISL95820 is a 1-, 2-, 3-, or 4-phase pwm controller for the intel microprocessor vr12.5 core voltage regulator. the ISL95820 is designed to be compliant to intel vr12.5 specifications with serialvid features. the smbus/pmbus/i 2 c can be programmed with the embedded controller. th e system parameters and svid required registers are programmable with two dedicated pins. this greatly simplifies the system design for various platforms and lowers inventory complexity and cost by using a single device. multiphase power conversion microprocessor load current profiles have changed to the point that the advantages of mult iphase power conversion are impossible to ignore. multiphase converters overcome the daunting technical challenges in producing a cost-effective and thermally viable single-phase converter. the ISL95820 controller reduces the complexity of multiphase implementation by integrating vital functions, including integrated drivers for three phases, direct interface for a fourth external driver device, and requiring minimal output compon ents. the ?typical application circuit? on page 7 provides the top level views of multiphase power conversion using the ISL95820 controller. interleaving the switching of each channel in a multiphase converter is timed to be symmetrically out-of-phase with the other channels. for the example of a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. as a result, the 3-phase converter has a combined ripple frequency three times that of the ripple frequency of any one phase, as illustrated in figu re 3. the three channel currents (il1, il2, and il3) combine to form the ac ripple current and to supply the dc load current. the ripple current of a multiphase converter is less than that of a single-phase converter supplying the same load. to understand why, examine equation 1, whic h represents an individual channel?s peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f sw is the switching frequency. in a multiphase converter, the output capacitor current is the superposition of the ripple current s from each of the individual phases. compare equation 1 to the expression for the peak-to-peak current after the summation of n (symmetrically phase-shifted inductor currents) in equation 2, the peak-to-peak overall ripple current (i c(p-p) ) decreases with the increase in the number of channels, as shown in figure 4, which introduces the concept of the ripple current multiplier (k rcm ). at the (steady state) duty cycles for which the ripple current, and thus the k rcm , is zero, the turn-off of one phase corresponds exactly with the turn-on of another phase, resulting in the sum of all ph ase currents being always the (constant) load current, and therefore there is no ripple current in this case. output voltage ripple is a function of capacitance, capacitor equivalent series resistance (e sr), and the summed inductor ripple current. increased ripple frequency and lower ripple amplitude mean that the designer can use lower saturation-current inductors and fewer or less costly output capacitors for any performance specification. i p-p v in v out ? () v out ? lf sw v ? in ? --------------------------------------------------------- - = (eq. 1) figure 3. pwm and inductor-current waveforms for 3-phase converter 1s/div pwm2, 5v/div pwm3, 5v/div il2, 7a/div il3, 7a/div il1 + il2 + il3, 7a/div il1, 7a/div pwm1, 5v/div duty cycle (v out /v in ) figure 4. ripple current mu ltiplier vs duty cycle ripple current multiplier, k rcm n=1 3 4 2 5 6
ISL95820 13 fn8318.0 february 4, 2013 another benefit of interleaving is to reduce the input ripple current. input capacitance is determined in part by the maximum input ripple current. multiphase topologies can improve overall system cost and size by lowe ring input ripple current and allowing the designer to reduce the cost of input capacitors. figure 5 example illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 5 delivers 36a to a 1.5v load from a 12v input. the rms input capacitor current is 5.9a. compare this to a single-phase converter also st epping down 12v to 1.5v at 36a. the single-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. a more detailed exposition of input capacitor design is provided in ?input capacitor selection? on page 20. multiphase r3? modulator the intersil ISL95820 multiphase regulator uses the patented r3? (robust ripple regulator?) modulator. the r3? modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their shortcomings. figure 6 shows the conceptual multiphase r3? modulator circuit, and figure 7 illustrates the operational principles. the internal modulator uses a master clock circuit to generate the clocks for the slave circuits, one per phase. the r3? modulator master oscillator slews between two voltage signals, the comp voltage (the output of the voltag e sense error amplifier) and vw (voltage window), a voltage positively offset from comp by an offset voltage that is dependent on the nominal switching frequency. the modulator discharges the master clock ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor, dependent on nominal switching frequency, and also on number of active phases. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets (charges quickly) to vw when it discharges (with discharge current g m v o ) to comp and generates a one-shot master clock signal. a phase sequencer distributes the master clock signal to the active slave circuits. if vr is in 4-phase mode, the master clock signal will be distributed to the four phases 90 out-of-phase, in 3-phase mode distributed to the three phases 120 out-of-phase, and in 2-phase mode distributed to phases 1 and 2 180 out-of-phase. if vr is in 1-phase mode, the master clock signal will be distributed to phase 1 only and will be the clock1 signal. each slave circuit has its own ripple capacitor c rsn , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage (or alternatively, series sense resistor voltage, indicative of th at phase?s inductor current) into a current source to charge and discharge c rsn . the slave circuit turns on its pwm pulse upon receiv ing its respective clock signal clock n , and the current source charges c rsn with a current proportional to its respective po sitive inductor voltage. when c rsn voltage v crsn rises to vw, the slave circuit turns off the pwm pulse, and the current source then discharges c rsn , with a current proportional to its respective no w-negative inductor voltage. c rsn discharges until the next clock n pulse, and the cycle repeats. since the modulator works with the v crs n , which are large-amplitude and noise-free sy nthesized signals, it achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the ISL95820 uses an error amplifier that allows the controller to maintain a 0.5% output voltage accuracy. (eq. 2) m roundup n d ? 0 , () = for m1 ? nd ? m ? i c(p-p) v out lf sw ? -------------------- k rcm = k rcm nd ? m ? 1 + () mnd ? () ? () ? nd ? ---------------------------------------------------------------------------- - = figure 5. channel input currents and input-capacitor rms current for 3-phase converter channel 3 input current 10a/div channel 2 input current 10a/div channel 1 input current 10a/div input-capacitor current, 10a/div 1s/div figure 6. r3 ? modulator circuit at 3-phase mode crm gmvo master clock vw comp master clock phase sequencer clock1 clock2 r i l1 gm clock1 phase1 crs1 vw s q pwm1 l1 r i l2 gm clock2 phase2 crs2 vw s q pwm2 l2 co vo vcrm vcrs1 vcrs2 master clock circuit slave circuit 1 slave circuit 2 r i l3 gm clock3 phase3 crs3 vw s q pwm3 l3 vcrs3 slave circuit 3 clock3
ISL95820 14 fn8318.0 february 4, 2013 figure 8 illustrates the operational principles during load insertion response. the comp volt age rises during load insertion (due to the sudden discharge of the output capacitor driving the inverting input of the error amplifier), generating the master clock signal more quickly, so th e pwm pulses turn on earlier, increasing the effective switching frequency. this phenomenon allows for higher control loop bandwidth than conventional fixed frequency pwm controllers. the vw voltage rises with the comp voltage, making the pwm on-time pulses wider. during load release response, the comp voltag e falls. it takes the master clock circuit longer to generate the next master clock signal so the pwm pulse is held off until needed. the vw voltage falls with the comp voltage, reducing the current pwm pulse width. the inherent pulse frequency and width increases due to an increasing load transient, and likewise the pulse frequency and width reductions due to a decreasing load transient, produce the excellent load transient response of the r3? modulator. since all phases share the same vw window (master clock frequency generator) and threshold (slave pulse width generator) voltage, dynamic current balance among phases is ensured, inherently, for the duration of any load transient event. the r3? modulator intrinsically has input voltage feed-forward control, due to the proportional dependence of the clock generator slave transconductance gains on the input voltage. this dependence decreases the on-time puls e-width of each phase in proportion to an increase in input voltage, making the output voltage insensitive to a fast slew rate input voltage change. diode emulation and period stretching the ISL95820 can operate in diode emulation mode (dem) to improve light load efficiency. diode emulation can be optionally enabled in ps2 and ps3, in phase-1 only operation, by selection of prog2 pin resistance to ground. in dem, the low-side mosfet conducts while the current is flowing from source to drain and blocks reverse current, emulating a diode. as illustrated in figure 9, when lgate is on, the low-side mosfet carries current, creating negative voltage on the phase node due to the voltage drop across the on-resistance. the controller mo nitors the inductor current by monitoring the phase node voltag e. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. if the load current is light enou gh, as figure 9 illustrates, the inductor current will reach and stay at zero before the next phase node pulse and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator will appear to operate in continuous conducti on mode (ccm), although the controller is nevertheless configured for dem. figure 10 shows the operation principle in diode emulation mode at light load. the load gets increm entally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size, making the inductor current triangle the same in the figure 7. r3 ? modulator operation principles in steady state at 3-phase mode comp vcrm master clock pwm1 vw clock1 pwm2 clock2 hysteretic window pwm3 vcrs3 clock3 vcrs2 vcrs1 vw figure 8. r3 ? modulator operation principles in load insertion response at 3-phase mode comp vcrm master clock pwm1 vcrs1 vw clock1 pwm2 vcrs2 clock2 pwm3 clock3 vcrs3 vw ugate phase il lgate figure 9. diode emulation
ISL95820 15 fn8318.0 february 4, 2013 three cases (only the time between inductor current triangles changes). the controller clamps the ripple capacitor voltage v crs in dem to make it mimic the inductor current. it takes the comp voltage longer to hit v crm , which produces master clock pulses, naturally stretching the switching period. the inductor current triangles move further apart from each other, such that the inductor current average value is equal to the load current. the reduced switching frequency improves light load efficiency. because the next clock pulse occurs when v comp (which tracks output voltage error) rises above v crm , dem switching pulse frequency is responsive to load transient events in a manner similar to that of mu ltiphase ccm operation. adaptive body diode conduction time reduction when in dcm, the controller ideally turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative by the product of the (negative) inductor current and the low-side mosfet r ds(on) , producing a voltage drop that is proportional to the inductor current. a phase comp arator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero-crossing point of the inductor current. if the inductor current has not reached zero when the low-side mosfet turns off, it will flow through the low-side mosfet body diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it will flow through the high-side mosfet body diode, causing the phase node to have a positive voltage spike (to v in plus a pn diode voltage drop) until the current decays to zero. the controller continues monitoring the phase voltage after turning off the low-side mosfet and adjusts the phase comparator th reshold voltage accordingly in iterative steps, such that the low-side mosfet body diode conducts for approximately 40ns (turning off 40ns before the inductor current zero-crossing) to minimize the body diode-related loss. modes of operation vr can be configured for 4-, 3-, 2-, or 1-phase operation. table 1 shows vr configurations and op erational modes, programmed by the isen4, isen 3 and isen2 pin status, and the set ps command. for the 3-phase configuration, tie the isen4 pin to 5v. in this configuration, phases 1, 2, and 3 are active. for the 2-phase configuration, tie the isen 3 and isen4 pin to 5v. in this configuration, phases 1 and 2 are active. for the 1-phase configuration, tie the isen4, isen 3, and isen2 pin to 5v. in this configuration, only phase 1 is active. in the 4-phase configuration, vr operates in 4-phase ccm in ps0. it enters 2-phase ccm mode in ps1 by dropping phases 4 and 3 and reducing the overcurrent protection level to 1/2 of the initial value. it enters 1-phase dem (optionally ccm) in ps2 and ps3 by dropping phases 4, 3, and 2, and reducing the overcurrent protection levels to 1/4 of the initial value. in the 3-phase configuration, vr operates in 3-phase ccm in ps0. (phase 4 is disabled). it enters 2-phase ccm mode in ps1 by dropping phase 3 and reducing the overcurrent protection level to 2/3 of the initial value. it enters 1-phase dem (optionally ccm) in ps2 and ps3 by dropping phases 3 and 2, and reducing the overcurrent and the protection level to 1/3 of the initial value. in the 2-phase configuration, vr operates in 2-phase ccm in ps0. (phases 4 and 3 are disabled.) it enters 1-phase mode in ps1, ps2, and ps3 by dropping phase 2 and reducing the overcurrent il il vcrs il vcrs vcrs vw ccm/dcm boundary light dcm deep dcm vw vw figure 10. period stretching table 1. vr modes of operation isen4 isen3 isen2 config. ps mode ocp threshold (a) to power stage to power stage to power stage 4-phase cpu vr config. 04-phase ccm 60 12-phase ccm 30 21-phase opt: dem or ccm 20 3 tied to 5v 3-phase cpu vr config. 03-phase ccm 60 12-phase ccm 40 21-phase opt: dem or ccm 20 3 tied to 5v 2-phase cpu vr config. 02-phase ccm 60 11-phase ccm 30 21-phase opt: dem or ccm 3 tied to 5v 1-phase cpu vr config. 01-phase ccm 60 1 21-phase opt: dem or ccm 3
ISL95820 16 fn8318.0 february 4, 2013 protection level to 1/2 of the initial value. ps1 operates in ccm, and ps2 and ps3 operate in dem (optionally ccm). in the 1-phase configuration, vr operates in 1-phase ccm in ps0 and ps1, and enters 1-phase dem (optionally ccm) in ps2 and ps3. the overcurrent protection level is the same for all power states. this information is summarized in table 1. programming resistors there are three programming resistors: r prog1 , r prog2 and r prog3 . table 2 shows how to select r prog1 based on vr i cc(max) register settings. determ ine the maximum current vr can support and set the vr i cc(max) register value accordingly, by selecting the appropriate r prog1 value. the cpu will read the vr i cc(max) register value and ensure that the cpu core current doesn?t exceed the value specified by vr i cc(max) . r prog2 sets the start-up (v boot ) voltage, and selects whether the droop (programmable dc loadline) fu nction is enabled on power-up, and whether diode emulation is enabled in ps2 and ps3. when the controller works in the targeted application with a cpu, select r prog2 , such that vr powers up to v boot =0v, as required by the svid command. in the absence of a cpu, such as testing of the vr alone, select r prog2 for v boot of 1.65v, 1.7v or 1.75v. table 3 shows how to select r prog2 to enable droop, select v boot , and select operational mode in ps2 and ps3 (ccm vs dem). note that the effective resistance value of the dc loadline, i.e., the output voltage droop due to load current, is determined by components of the output current sense, voltage feedback, and modulator compensation networks. switching frequency selection there are a number of variables to consider when choosing the switching frequency, as there ar e considerable effects on the upper-mosfet loss calculation. these effects are outlined in ?mosfets? on page 17, and they establish the upper limit for the switching frequency. the lower limit is established by the requirement for fast transient re sponse and small output-voltage ripple as outlined in ?output filter design? on page 20. choose the lowest switching frequency that a llows the regulator to meet the transient-response and output -voltage ripple requirements. the resistor from prog3 to gnd selects one of three available switching frequencies, 200khz, 300khz, and 450khz, and sets the modulator slope compensation value. note that when the ISL95820 is in continuous conduc tion mode (ccm), the switching frequency is not strictly constant due to the nature of the r3? modulator. as explained in ?multiphase r3? modulator? on page 13, the effective switching frequency will increase during load insertion and will decrease during load release to achieve fast response. however, the switching frequency is nearly constant at constant load. variation is expected when the power stage condition, such as input volt age, output voltage, load, etc. changes. the variation is usually less than 15% and doesn?t have any significant effect on output voltage ripple magnitude. table 4 shows how to select r prog3 to obtain the desired modulator slope table 2. prog1 programming table r prog1 (k ? ) eia e96 1% value vr i cc(max) (a) 3.24 15 5.76 20 9.53 25 13.3 30 16.9 35 21.0 40 24.9 45 28.7 50 34.0 55 42.2 60 49.9 65 57.6 70 64.9 75 73.2 80 80.6 90 88.7 100 100 115 113 130 124 145 137 160 154 180 169 200 187 225 221 225 table 3. prog2 programming table r prog2 (k ? ) eia e96 1% value droop enabled operational mode in ps2 and ps3 v boot (v) 3.24 yes dem 0 5.76 yes dem 1.65 9.53 yes dem 1.7 13.3 yes dem 1.75 16.9 yes ccm 1.75 21.0 yes ccm 1.7 24.9 yes ccm 1.65 28.7 yes ccm 0 34.0 no dem 0 42.2 no dem 1.65 49.9 no dem 1.7 57.6 no dem 1.75 64.9 no ccm 1.75 73.2 no ccm 1.7 80.6 no ccm 1.65 88.7 no ccm 0
ISL95820 17 fn8318.0 february 4, 2013 compensation and switching frequency. there are many choices of slope compensation for each switching frequency. general design guide this design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. it is assumed that the reader is familia r with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complete reference designs, which include schematics, bill of materials, and example board layouts for common microprocessor applications. power stages the first step in designing a multiphase converter is to determine the number of phases. this dete rmination depends heavily upon the cost analysis, which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power supply circuitry. generally sp eaking, the most economical solutions are those in which each phase handles between 15a and 25a. all surface-mount design s will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to conduct; the swit ching frequency; the capability of the mosfets to dissipate heat; and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for heat dissipated in the lower (alternatively called low-side) mosfet of each phase is simple, since virtually all of the heat loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 3, i m is the maximum continuous output current; i p-p is the peak-to-peak inductor current per phase (see equation 1 on page 12); d is the duty cycle (v out /v in ); and l is the per-channel inductance. equation 3 shows the approximation . a term can be added to the lower-mosfet loss equation to account for the loss during the de ad time when inductor current is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) ; the switching frequency, f sw ; and the length of dead times (t d1 and t d2) at the beginning and the end of the lower-mosfet conduction interval respectively. finally, the power loss of output capacitance of the lower mosfet is approximated in equation 5: where c oss_low is the output capacitance of lower mosfet at the test voltage of v ds_low . depending on the amount of ringing, the actual power dissipation will be slightly higher than this. thus the total maximum power dissipated in each lower mosfet is approximated by the summation of p low,1 , p low,2 and p low,3 . upper mosfet power calculation in addition to r ds(on) losses, a large portio n of the upper-mosfet losses are due to currents cond ucted across the input voltage (v in ) during switching. since a substa ntially higher portion of the upper-mosfet losses are dependen t on switching frequency, the power calculation is more comple x. upper mosfet losses can be divided into separate componen ts involving the upper-mosfet switching times; the lower-mosfet body-diode reverse-recovery charge, q rr ; and the upper mosfet r ds(on) conduction loss. table 4. prog3 programming table r prog3 (k ? ) eia e96 1% value slope compensation switching frequency (khz) 3.24 0.25x 200 5.76 0.5x 200 9.53 0.75x 200 13.3 1x 200 16.9 1.25x 200 21.0 1.5x 200 24.9 1.75x 200 34.0 0.25x 300 42.2 0.5x 300 49.9 0.75x 300 57.6 1x 300 64.9 1.25x 300 73.2 1.5x 300 80.6 1.75x 300 88.7 2x 300 100 0.25x 450 113 0.5x 450 124 0.75x 450 137 1x 450 154 1.25x 450 169 1.5x 450 187 1.75x 450 221 2x 450 p low 1 , r ds on () i m n ----- - 2 i p-p 2 12 ---------- +1d ? () ? = (eq. 3) p low 2 , v don () f sw i m n ----- - i p-p 2 ---------- ? ?? ?? ?? t d1 i m n ----- - i p-p 2 ---------- ? ?? ?? ?? t d2 + = (eq. 4) p low 3 , 2 3 -- - v in 1.5 c oss_low v ds_low f sw ?? ? ? (eq. 5)
ISL95820 18 fn8318.0 february 4, 2013 when the upper mosfet turns off, the lower mosfet does not conduct any portion of the induct or current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 6, the required time for this commutation is t 1 and the approximated associated power loss is p up(1) . at turn on, the upper mosfet begins to conduct and this transition occurs over a time (t 2 ). in equation 7, the approximate power loss is p up(2) . a third component involves the lower mosfet?s reverse-recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower-mo sfet?s body diode can draw all of q rr , it is conducted through the upper mosfet across v in . the power dissipated as a result is p up(3) and is approximated in equation 8: the resistive part of the upper mo sfet is given in equation 9 as p up(4) . equation 10 accounts for some power loss due to the drain-source parasitic inductance (l ds , including pcb parasitic inductance) of the upper mosfet, although it is not exact: finally, the power loss of output capacitance of the upper mosfet is approximated in equation 11: where c oss_up is the output capacitance of the lower mosfet at test voltage of v ds_up . depending on the amount of ringing, the actual power dissipation will be slightly higher than this. the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 6 through 11. since the power equations depend on mosfet parameters, choosing the correct mosfet can be an iterative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. integrated driver operation and adaptive shoot-through protection the ISL95820 provides three integrated mosfet drivers, for phases 1 through 3, and a pwm signal to operate a single external driver device, required if a fourth phase is required. designed for high-speed switching, the intern al mosfet drivers control both high-side and low-side n-channel fets from the internal pwm signal a rising transition on the internal pwm signal (phases 1 through 3) initiates the turn-off of th e lower mosfet. after a short propagation delay [t pdll ], the lower gate begins to fall. following a 25ns blanking period, adaptive shoot-through circuitry monitors the lgate voltage and turns on the upper gate following a short delay time [t pdhu ] after the lgate voltage drops below ~1.75v. the upper gate drive then begins to rise [t ru ] and the upper mosfet turns on. a falling transition on the intern al pwm signal indicates the turn- off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlu ] is encountered before the upper gate begins to fall [t fu ]. the adaptive shoot-through circuitry monitors the ugate-phase voltage and turns on the lower mosfet a short delay time [t pdhl ] after the upper mosfet?s phase voltage drops below +0.8v or 40ns after the upper mosfet?s gate voltage [ugate-phase] drops below ~1.75v. the lower gate then rises [t rl ], turning on the lower mosfet. these methods prevent both the lower and upper mosfets from conducting simultaneously (shoot -through), while adapting the dead time to the gate charge characteristics of the mosfets being used. the internal drivers are optimized for voltage regulators with large step down ratio. the lower mosfet is usually sized larger compared to the upper mosfet because the lower mosfet conducts for a longer time during a switching period. the lower gate driver is therefore sized much larger to meet this application requirement. the 0.8 on-resistance and 3a sink current capability enable the lower gate driver to absorb the current injected into the lower gate through the drain-to-gate capacitor of the lower mosfet and help prevent shoot-through caused by the self turn-on of the lower mosfet due to high dv/dt of the switching node. for vccp < 7v, diode emulation mode (dem) must be disabled using the prog2 pin programming resistor. internal bootstrap device the integrated drivers feature an internal bootstrap schottky diode equivalent circuit implemen ted by switchers with a typical on-resistance of 40 and without the typical diode forward voltage drop. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap function is also desi gned to prevent the bootstrap capacitor from overcharging due to the large negative swing at the trailing-edge of the phase node. this reduces the voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating well above the maximum voltage intended for uvcc. its minimum capacitance value can be estimated using equation 12: p up 1 () v in i m n ----- - i p-p 2 ---------- + ?? ?? t 1 2 ---- ?? ?? ?? f sw (eq. 6) p up 2 () v in i m n ----- - i p-p 2 ---------- ? ?? ?? ?? t 2 2 ---- ?? ?? ?? f sw (eq. 7) p up 3 () v in q rr f sw = (eq. 8) (eq. 9) p up 4 () r ds on () i m n ----- - ?? ?? ?? 2 i p-p 2 12 ---------- +d ? p up 5 () l ds i m n ----- - i p-p 2 ---------- + ?? ?? ?? 2 (eq. 10) p up 6 () 2 3 -- - v in 1.5 c oss_up v ds_up f sw ?? ? ? (eq. 11)
ISL95820 19 fn8318.0 february 4, 2013 where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. select results are exemplified in figure 11. . power dissipation in the integrated drivers internal driver power dissipation is mainly a function of the switching frequency (f sw ), the output drive im pedance, the layout resistance, and the selected mosfet?s internal gate resistance and total gate charge (q g ). calculating the power dissipation in the driver for a desired application is cr itical to ensure safe operation. exceeding the maximum allowable power dissipation level may push the ic beyond the ma ximum recommended operating junction temperature. the dfn package is more suitable for high frequency applications. the total gate drive power losses due to the gate charge of mosfets and th e driver?s internal circuitry and their corresponding average driver current, per driver, can be estimated using equations 13 and 14, respectively: where the gate charge (q g1 and q g2 ) is defined at a particular gate-to-source voltage (v gs1 and v gs2 ) in the corresponding mosfet datasheet; i q is the driver?s total quiescent current with no load at both drive outputs; n q1 and n q2 are the number of, and uvcc and lvcc are the drive voltages for, the upper and lower mosfets, respectively. the i q* v ccp product is the quiescent power of the driver without a load. the total gate drive power losses are dissipated among the resistive components along the transition path, as outlined in equation 15. the drive resistance dissipates a portion of the total gate drive power losses; the rest will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of mosfets. figures 12 and 13 show the typical upper and lower gate drives turn-on current paths. . upper mosfet self turn-on effect at start-up should a driver have insufficient bias voltage applied (at pin vccp), its outputs are floating. if the input bus is energized at a high dv/dt rate while the driver outputs are floating, due to self-coupling via the internal c gd of the mosfet, the gate of the upper mosfet could momentarily rise up to a level greater than the threshold voltage of the devi ce, potentially turning on the upper switch. therefore, if such a situation could conceivably be encountered, it is a common pr actice to place a resistor (r ugph ) c boot_cap q ugate v boot_cap -------------------------------------- q ugate q g1 uvcc ? v gs1 ----------------------------------- - n q1 ? = (eq. 12) 50nc 20nc figure 11. bootstrap capacitance vs boot ripple voltage v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q ugate = 100nc p qg_tot p qg_q1 p qg_q2 i q vcc ? p ++ = (eq. 13) p qg_q1 q g1 uvcc 2 ? v gs1 --------------------------------------- f sw ? n q1 ? = p qg_q2 q g2 lvcc 2 ? v gs2 -------------------------------------- f sw ? n q2 ? = i dr q g1 uvcc n q1 ? ? v gs1 ----------------------------------------------------- - q g2 lvcc n q2 ? ? v gs2 ---------------------------------------------------- - + ?? ?? ?? f sw i q + ? = (eq. 14) figure 12. typical upper-gate drive turn-on path figure 13. typical lower-gate drive turn-on path p dr p dr_up p dr_low i q vcc ? ++ = (eq. 15) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 2 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = q1 d s g r g1 r l1 boot r hi1 c ds c gs c gd r lo1 phase vccp vccp q2 d s g r g2 r l2 r hi2 c ds c gs c gd r lo2
ISL95820 20 fn8318.0 february 4, 2013 across the gate and source of th e upper mosfet to suppress the miller coupling effect. the value of the resistor depends mainly on the input voltage?s rate of rise, the c gd /c gs ratio, as well as the gate-source threshold of the upper mosfet. a higher dv/dt, a lower c ds /c gs ratio, and a lower gate-source threshold upper fet will require a smaller resistor to diminish the effect of the internal capacitive coupling. for most applications, the integrated 20k resistor is sufficient, not affecting normal performance and efficiency. the coupling effect can be roughly estimated with equation 16, which assumes a fixed linear input ramp and neglects the clamping effect of the body di ode of the upper drive and the bootstrap capacitor. other parasitic components such as lead inductances and pcb capacitances are also not taken into account. figure 6 provides a visual reference for this phenomenon and its potential solution. external (phase 4) driver selection when a fourth phase is to be us ed, it is recommended that the intersil isl6625a driver be selected as the external phase 4 driver device. output filter design the output inductors and the outp ut capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. the ou tput filter also must provide the transient energy until the re gulator can respond. because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. the output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the outp ut capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, i; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, v max . capacitors are characterized according to their capacitance, equivalent series resistance (esr), and equivalent series inductance (esl). at the beginning of the load transi ent, the output capacitors supply all of the transient current. the output voltage will initially deviate by an amount approximated by the vo ltage drop across the esl. as the load current increases, the volt age drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output-voltage deviation is less than the allowable maximum. neglecting the contribution of inductor current and regulator response, the output voltage initia lly deviates by an amount, as shown in equation 17: the filter capacitor must have sufficiently low esl and esr so that v < v max . most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors, allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors, allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current (see ?interleaving? on page 12 and equation 2), a voltage develops across the bulk-capacitor esr equal to i c(p-p) (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) , determines a lower limit on the inductance, as shown in equation 18. since the capacitors are supplying a decreasing portion of the load current while the regulator re covers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than v max . this places an upper li mit on inductance. equation 19 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 20 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be selected base d on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capacity must be sufficient to handle the ac component of the current drawn by the upper mosfets, which is related to duty cycle and the number of active phases. the input rms current can be calculated with equation 21.. v gs_miller dv dt ------- rc rss 1e v ? ds dv dt ------- rc ? iss ? --------------------------------- - ? ?? ?? ?? ?? ?? ?? ?? = rr ugph r gi + = c rss c gd = c iss c gd c gs + = (eq. 16) vesl () di dt ---- - esr () i + (eq. 17) l esr v out k rcm ? f sw v in v ? p-p max () ? ------------------------------------------------------------ ? (eq. 18) l 2ncv ? out ?? i () 2 ----------------------------------------- v max i esr ? ? (eq. 19) l 1.25 nc ?? i () 2 ---------------------------- - v max i esr ? ? v in v out ? ?? ?? (eq. 20) i in rms () k in cm () 2 io 2 ? k ramp cm () 2 i lo(p-p) 2 ? + = (eq. 21)
ISL95820 21 fn8318.0 february 4, 2013 for a 2-phase design, use figure 14 to determine the input capacitor rms current requirement given the duty cycle, maximum sustained output current (i o ), and the ratio of the per-phase peak-to-peak inductor current (i l(p-p) ) to i o . select a bulk capacitor with a ripple current rating, which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25x greater than the maximum input voltage. figures 15 and 16 provide the same input rms current information for 3- and 4-phase designs, respectively. use the same approach to selecting the bulk capacitor type and number, as previously described. low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. the result from the high current slew rates produced by the upper mosfets turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitic impedances and maximize noise suppression. multiphase rms improvement figure 17 is provided as a refe rence to demonstrate the dramatic reductions in input-capacitor rms current upon the implementation of the multiphase topology. for example, compare the input rms current requirements of a 2-phase converter versus that of a single-phase. assume both converters have a duty cycle of 0.25, maxi mum sustained output current of 40a, and a ratio of i l(p-p) to i o of 0.5. the single-phase converter would require 17.3a rms current capacity, while the 2-phase converter would only require 10.9a rms . the advantages become even more pronounced when ou tput current is increased and additional phases are added to keep the component cost down relative to the single-phase approach. k in cm () nd ? m ? 1 + () mnd ? ? () ? n 2 --------------------------------------------------------------------------- - = (eq. 22) k ramp cm () m 2 nd ? m ? 1 + () 3 m1 ? () 2 mnd ? ? () 3 + 12n 2 d 2 ------------------------------------------------------------------------------------------------------------------ = (eq. 23) 0.3 0.1 0 0.2 input-capacitor current (i rms /i o ) figure 14. normalized input- capacitor rms current vs duty cycle for 2-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v out /v in ) i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o duty cycle (v out /v in ) figure 15. normalized input- capacitor rms current vs duty cycle for 3-phase converter 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms/ i o ) 0.3 0.1 0 0.2 i l(p-p) = 0 i l(p-p) = 0.25 i o i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o input-capacitor current (i rms/ i o ) figure 16. normalized input- capacitor rms current vs duty cycle for 4-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v out /v in ) 0.3 0.1 0 0.2 i l(p-p) = 0 i l(p-p) = 0.25 i o i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o figure 17. normalized input-capacitor rms current vs duty cycle for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v out /v in ) input-capacitor current (i rms/ i o ) 0.6 0.2 0 0.4 i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o
ISL95820 22 fn8318.0 february 4, 2013 inductor current sensing and balancing inductor dcr current-sensing network figure 18 shows the inductor dcr current-sensing network for the example of a 3-phase voltage regulator. an inductor?s current flows through the inductor?s dcr and creates a voltage drop. each inductor has two resistors, r sum and r o , connected to the pads to accurately sense the inductor current by sensing the dcr voltage drop. the r sum and r o resistors are connected in a summing network as shown, and feed the total current information to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to compensate for the change in inductor dcr due to temperature changes. the inductor output side pads are electrically shorted in the schematic, but have some parasitic impedance in actual board layout, which is why one cannot simply short them together for the current-sensing summing network. it is recommended to use 1 ? ~10 ? r o to create quality signals. since the r o value is much smaller than the rest of the current sensing circuit, the following analysis will ignore it for simplicity. the summed inductor current information is presented to the capacitor c n . equations 24 thru 28 describe the frequency-domain relationship between inductor total current i o (s) and c n voltage v cn (s): where n is the number of phases. the inductor dcr value increases as the inductor temperature increases, due to the positive temperature coefficient of the copper windings. if uncompensated, this will cause the estimate of inductor current to increase with temperature. the resistance of the co-located ntc thermistor, r ntc , decreases as its temperature increases, compensating for the increase in dcr. proper selections of r sum , r ntcs , r p and r ntc parameters ensure that v cn represents the inductor total dc current over the temperature range of interest. there are many sets of parameters that can properly temperature-compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltage. it is recommended to have a high ratio of v cn to the inductor dcr voltage, so the current sense circuit has a higher sign al level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 3.65k ? , r p =11k ? , r ntcs = 2.61k ? and r ntc = 10k ? (ert-j1vr103j). the ntc network parameters may need to be fine tuned on actual boards. one can apply full load dc current and record the output voltage reading immediately; then record the ou tput voltage reading again when the board has reached the thermal steady state. a good ntc network can limit the output voltag e drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current-sensing network parameters to minimize engineering time. v cn (s) response must track i o (s) over a broad range of frequency for the controller to achieve good transient response. transfer function a cs (s) (equation 29) has unity gain at dc, a pole sns, and a zero l . to obtain unity gain at all frequencies, set l equal to sns and solve for cn. for example, given n = 3, r sum = 3.65k ? , r p = 11k ? , r ntcs =2.61k ? , r ntc = 10k ? , dcr = 0.9m ? and l = 0.36h, equation 29 gives c n =0.397f. assuming the loop compensator design is correct, figure 26 shows the expected load transient response waveforms for the correctly chosen value of c n . when the load current i core has a step change, the output voltage v core also has a step change, determined by the dc loadline re sistance (the output voltage droop value of the regulator, (see ?current sense circuit cn rsum ro rntcs rntc rp dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isump isumn vcn figure 18. dcr current-sensing network v cn s () r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ?? ?? ?? ?? ?? i o s () a cs s () = (eq. 24) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ ---------------------------------------------------- = (eq. 25) a cs s () 1 s l ------ - + 1 s sns ------------ - + ---------------------- - = (eq. 26) l dcr l ------------- = (eq. 27) sns 1 r ntcnet r sum n -------------- - r ntcnet r sum n -------------- - + ------------------------------------------ c n -------------------------------------------------------- = (eq. 28) c n l r ntcnet r sum n -------------- - r ntcnet r sum n -------------- - + ------------------------------------------ dcr -------------------------------------------------------------- - = (eq. 29)
ISL95820 23 fn8318.0 february 4, 2013 adjustments? on page 28). if the c n value is too large or too small, v cn (s) will not accurately represent real-time i o (s) and will worsen the transient response. figure 28 shows the load transient response when c n is too small. v core will droop excessively, briefly, upon abrupt load insertion, before recovering to the intended dc value, which may create a system failure. there wi ll be excessive overshoot during load decreases, which may potentially hurt the cpu reliability. with the proper selection of c n , assume that a cs (s) = 1. with this assumption, equation 29 can be recast as equation 30: with a properly designed inductor temperature compensation network, we may also assume the room temperature inductor dcr value together with the room temperature value of r ntcnet in subsequent calculations, since any temperature variation in one value will be, ideally, exactly compensated by a variation in the other value. equation 31 can be evaluated, using room temperature resistance values, to obtain a constant value of the ratio v cn /i o , in units of resistance, for a given dcr current sense network design. this constant value, designated , will be required to complete the regulator design. this expression applies to th e dcr current sense circuit of figure 18. figure 19 shows the resistor current-sensing network for the example of a 3-phase regulator. each inductor has a series current-sensing resistor r sen . r sum and r o are connected to the r sen pads to accurately capture the inductor current information. the r sum and r o resistors are connected to capacitor c n . r sum and c n form a filter for noise attenuation. equations 32 thru 34 give v cn (s) expression: resistor current-sensing network transfer function a rsen (s) always has unity gain at dc. current-sensing resistor r sen value will not have significant variation over-temperature, so there is no need for the ntc network. the recommended values are r sum = 1k ? and c n = 5600pf. as with the dcr current sense netw ork, equation 34 can be recast as equation 35: this equation can be evaluated to obtain a constant value of the ratio v cn /i o , in units, for a given sense-resistor current sense network design. this constant value will be designated in v cn i o ---------- - r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ?? ?? ?? ?? ?? = (eq. 30) u o r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ?? ?? ?? ?? ?? roomtemp = (eq. 31) v cn s () r sen n ------------- i o s () a rsen s () = (eq. 3 a rsen s () 1 1 s rsen ----------------- + --------------------------- = (eq. 3 z rsen 1 r sum n -------------- - c n ---------------------------- - = (eq. 3 figure 19. resistor current-sensing network cn rsum ro dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isump isumn vcn rsen rsen rsen v cn i o ---------- - r sen n ------------- = (eq. 35)
ISL95820 24 fn8318.0 february 4, 2013 equation 36. as with the dcr-sense design, this constant value will be required to complete the regu lator design. this expression applies to the resistor curren t sense circuit of figure 19. programming of output overcurrent protection, i droop , and imon the final step in designing the current sense network is the selection of resistor ri of fi gures 18 or 19. this resistor determines the ratio of the controller?s internal representation of output current (i droop , also called the ?droop current?) to the actual output current, that is, to the sum of all the measured inductor currents. this internal representation is itself a current that will be used (a) to compare to the overcurrent protection threshold, (b) to drive the imon pi n external resistor to produce a voltage to represent the output current, which is measured and written to the iout register, and (c) to source the i droop current to the fb pin to provide the programmable load-dependent output voltage ?droop?, or output dc loadline. begin by selecting the maximum current that the regulator is designed to provide. this will be the value of vr i cc(max) programmed with the prog1 pin resistance to ground, as per table 2 on page 16. select r prog1 to program the lowest available value of i cc(max) that exceeds the expected maximum load. the overcurrent protection (ocp) threshold i ocp must exceed this value. i ocp is typically chosen to be 20% to 25% greater than i cc(max) . i ocp will determine the value of ri. refer to table 1 on page 15. the value of ocp threshold for any phase configuration (1- through 4-phase regulator) and any powerstate (ps0-ps3) is the value of i droop that will trigger output overcurrent protection. notice that the ocp threshold value of the ps0 row of any ph ase configuration is 60a. ri should be chosen, such that i droop will be 60a when the regulator output current is equal to the chosen value of output i ocp . the mechanism by which ri determines i droop is illustrated in figure 20. the isum transconductance amplif ier produces the current that drops the voltage v cn across ri, to make v isump = v isumn . this current is mirrored 1:1 to produce i droop , and 4:1 to produce i imon . i droop is compared directly to the ocp threshold, always 60a in ps0, so ri must be chosen to obtain the desired i ocp using equation 37: where o is the constant value determined in equations 31 or 36. for a given value of output current, i o , i droop will have the value: i droop is also used to program the slope of the output dc loadline. the dc loadline slope is the programmable regulator output resistance. the iout register will contain an 8-bit unsigned number indicative of the imon pin voltage, scaled such that its value is 00h when v imon = 0v, and ffh when v imon = 1.2v. with ri determined, r imon is chosen, such that v imon = 1.2v when the regulator load current is equal to i cc(max) , the maximum current value programmed by r prog1 . select r imon using equation 39: where again o is the constant value determined in equations 31 or 36. programming the dc loadline the dc loadline is the effective dc series resistance of the voltage regulator output. the output series resistance causes the output voltage to ?droop? below the selected regulation voltage by a voltage equal to the load current multiplied by the output resistance. the linear relationship of output voltage drop to load current is called the loadline, and is expressed in units of resistance. it will be designated r ll . figure 21 shows the equivalent circuit of a voltage regulator (vr) with the droop function. an ideal vr is equivalent to a voltage source (v = vid) and output impedance z out (s). if z out (s) is equal to the load line slope r ll , i.e., constant output impedance independent of frequency, v o will have step response when i o has a step change. the ISL95820 provides programm able dc loadline resistance. this feature can be disabled by choice of the programming resistor on pin prog2, or disabled via the serial bus. a typical desired value of the dc loadline for intel vr12.5 applications is r ll = 1.5m . the programmable dc loadline mechanism is integral to the regulator?s output voltage feedback compensator. this is illustrated in the feedback circuit and recommended o r sen n ------------- = (eq. 36) g m imon 11 1 / 4 adc cn v cn ... ... ri i sumn i sump i out register i droop r imon figure 20. ri o i ocp 60 a -------------- - = (eq. 37) i droop o ri ----- - i o = (eq. 38) r imon 1.2v o i cc max () ri 4 -------------------------- ?? ?? 1 ? = (eq. 39) figure 21. voltage regulator equivalent circuit o i v o vid z out (s) = r ll load vr
ISL95820 25 fn8318.0 february 4, 2013 compensation network shown in figure 22. the ISL95820 implements the dc loadline by injecting a current, i droop , which is proportional to the regulator output current i out , into the voltage feedback node (the fb pin). the scaling of i droop with respect to i out was selected in the previous section to obtain the desired output i ocp threshold. the droop voltage is the voltage drop across th e resistance, called r droop , between the fb pin and the output voltage due to i droop . r droop will be selected to implement the desired dc loadline resistance r ll . the fb pin voltage is thus raised above v out by the droop voltage, requiring the regulator to reduce v out to make v fb equal to the voltage regulator reference voltage applied to the error amplifier non-inverting input. r droop is a component of the voltage regulator stability compensation network. regulator stability and dynamic response are somewhat insensitive to the value of r droop , since a parallel series-rc will dominate the compensator response at, and well below, the open loop crossover frequency. but r droop plays a singular role in determining the dc loadline, and so will be chosen solely for that purpose. for a desired r ll , the output voltage reduction, v droop , due to an output load current, i o , is as shown by equation 40. the value of v droop obtained from the ISL95820 controller is the droop current, i droop , multiplied by the droop resistor, r droop . using equation 41, this value is as shown by equation 41. equate these two expressions for v droop and solve for r droop to obtain the value in equation 42. phase duty cycle balancing to equally distribute power dissipation between the phases, the ISL95820 provides a means to redu ce the deviatio n of the duty cycle of each phase from the average of all phases. the controller achieves duty cycle balance by matching the isen n pin voltages. the connection of these pins to their respective phase nodes is depicted in figure 23 for the inductor dcr current sense method. the current balancing meth ods described in this section apply also to current sensing using discrete sense resistors. the phase nodes have high amplitude square-wave voltage waveforms, for which the comparative duty cycle is indicative of each phase?s relative contribution to the output. r isen and c isen form lowpass filters to remove the switching ripple of the phase node voltages, such that the average voltages at the isen n pins approximately indicate each phase?s duty cycle, and thus the relative contribution of each ph ase. the controller gradually, and continually, trims the r3? modulator slave circuits, such that the relative duty cycle of each phase, as indicated by each v isen n , is equal to the others. this adjustment occurs slowly compared to the dynamic response of the mu lti-phase modulator to output voltage commands, load transients, and other system perturbations. it is recommended to use a large r isen c isen time constant, such that the isen n voltages have small ripple and are representative of the average or steady-state contribution of each phase to the output. recommended values are r isen =10k ? and c isen = 0.22f. ideally, balancing the phase duty cycles will also balance the output current provided by each phase, and thus the power dissipated in each phase?s components. this will be the case if the current sense elements of each phase are identical (dcr of the inductors, or discrete cu rrent sense resistors, and the associated current sense networks ), and if parasitic resistances of the circuit board traces from the sense connections to the common output voltage node are identical. figure 23 includes figure 22. differential voltage sensing and load line implementation x 1 e/a dac vid r droop i droop vdac v droop fb comp vcc sense = vout vss sense vids rtn vss internal to ic ?catch? resistor ?catch? resistor vr local vout v droop r ll i o = (eq. 4 r droop ri r ll o ---------------------- - = (eq. 42) v droop i droop r droop o ri ----- - i o r droop = = (eq. 4 figure 23. current balancing circuit internal to ic v o isen3 l3 risen cisen isen2 risen cisen isen1 risen cisen l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 v3p v2p v1p
ISL95820 26 fn8318.0 february 4, 2013 the printed circuit trace resist ances from each phase to the common output node. if these tr ace resistances are all equal, then the ideal of phase current balance will be achieved. this balance assumes the inductors and other current sense components are identical, comparing each phase to the others, a true assumption within the pu blished tolerance of component parameters. figure 23 includes the trace-resistance from each inductor to a single common output node. note that each r isen connection (v1p, v2p, and v3p) should be routed to its respective inductor phase-node-side pad in order to el iminate the effect of phase node parasitic pcb resistance from the switching elements to the inductor. equations 43 thru 45 give the isen pin voltages: where r dcr1 , r dcr2 and r dcr3 are the respective inductor dcrs; r pcb1 , r pcb2 and r pcb3 are the respective parasitic pcb resistances between the inductor output-side pad and the output voltage rail; and i l1 , i l2 and i l3 are inductor average currents. the controller will adjust the ph ase pulse-width relative to the other phases to make v isen1 =v isen2 =v isen3 , thus to achieve i l1 =i l2 =i l3 , when there are r dcr1 =r dcr2 =r dcr3 and r pcb1 =r pcb2 =r pcb3 . since using the same components fo r l1, l2 and l3 will typically provide a good match of r dcr1 , r dcr2 and r dcr3 , board layout will determine r pcb1 , r pcb2 and r pcb3 , and thus the matching of current per phase. it is recommended to have symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that r pcb1 =r pcb2 =r pcb3 . while careful symmetrical layout of the circuit board can achieve very good matching of these trac e resistances, such layout is often difficult to achieve in prac tice. if trace resistances differ, then exact matching the duty cycles of the phases will result in the imbalance of the phase currents. a modification of this circuit (to couple the signals of all the phases in the isen n networks), can correct the current imbalance due to unequal trace resistances to the output. for the example case of a 3-ph ase configuration, figure 24 shows the current balancing ci rcuit with the recommended trace-resistance imbalance correction. as before, v1p, v2p, and v3p should be routed to their respective inductor phase-node-side pads in order to eliminate the effect of phase node parasitic pcb resistance from the switching elements to each inductor. the sensing traces for v1n, v2n, and v3n should be routed to the v out output-side inductor pads so they indicate the voltage due only to the voltage drop across the inductor dcr, and not due to the pcb trace resistance. each isen pin sees the average voltage of three sources: its own phase inductor phase-node pa d, and the other two phases inductor output-side pads. equations 46 thru 48 give the isen pin voltages: the controller will make v isen1 = v isen2 = v isen3 , resulting in the equalities shown in equations 49 and 50: v isen1 r dcr1 r pcb1 + () i l1 vo + = (eq. 43) v isen2 r dcr2 r pcb2 + () i l2 vo + = (eq. 44) v isen3 r dcr3 r pcb3 + () i l3 vo + = (eq. 45) figure 24. differential-sensin g current balancing circuit internal to ic v o isen3 l3 risen cisen isen2 risen cisen isen1 risen cisen l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 risen risen risen risen risen risen v3p v3n v2p v2n v1p v1n v isen1 v 1p v 2n v 3n ++ () 3 ------------------------------------------------ - = (eq. 46) v isen2 v 1n v 2p v 3n ++ () 3 ------------------------------------------------ - = (eq. 47) v isen3 v 1n v 2n v 3p ++ () 3 ------------------------------------------------ - = (eq. 48) v 1p v 2n v 3n ++ v 1n v 2p v 3n ++ = (eq. 49) v 1n v 2p v 3n ++ v 1n v 2n v 3p ++ = (eq. 50)
ISL95820 27 fn8318.0 february 4, 2013 simplifying equation 49 gives equation 51: and simplifying equation 50 gives equation 52: combining equations 51 and 52 gives equation 53: which produces the desired result in equation 54: current balancing (i l1 =i l2 =i l3 ) will be achieved independently of any mismatch of r pcb1 , r pcb2 , and r pcb3 , to within the tolerance of the resistance of the current sense elements. note that with the crosscoupling of figure 25, the phase balancing circuit no longer seeks to equalize the duty cycles of the phases, but rather to equalize the dc components of the voltage drops across the current sense elements. small absolute differences in pcb trace resistance from the inductors to the common output no de, can result in significant phase current imbalance. it is strongly recommended that the resistor pads and connections for the current balancing method be included in any pcb layout. the decision to include the additional nx(n-1) trace-resistan ce-correcting resistors can then be deferred until the extent of the current imbalance can be measured on a functioning circui t. considerations for making this decision are described in ?current sense offset error? on page 28. with the isen n phase balancing mechanism (with cross coupling resistors if needed, or without if not needed), the r3? modulator achieves excellent current balancing during both steady state and transient operation. figu re 25 shows current balancing performance of an evaluation board with load transient of 12a/51a at different rep rates. the inductor currents follow the load current dynamic change with the output capacitors supplying the difference. the inductor currents can track the load current well at low rep rate, but cannot track the load when the rep rate gets into the hundred-kh z range, which is outside of the control loop bandwidth. regardless, the controller achieves excellent current balancing in all cases. v 1p v 1n ? v 2p v 2n ? = (eq. 51) v 2p v 2n ? v 3p v 3n ? = (eq. 52) v 1p v 1n ? v 2p v 2n ? v 3p v 3n ? == (eq. 53) r dcr1 i l1 r dcr2 i l2 r dcr3 i l3 == (eq. 54) figure 25. current balancing during dynamic operation. ch1: il1, ch2: i load , ch3: il2, ch4: il3 rep rate = 10khz rep rate = 25khz rep rate = 50khz rep rate = 100khz rep rate = 200khz
ISL95820 28 fn8318.0 february 4, 2013 current sense circuit adjustments once the voltage regulator is desi gned and a functional prototype has been assembled, adjustments may be necessary to correct for non-ideal components, or assembly and printed circuit board parasitic effects. these are effects that are usually not known until the design has been real ized. the following adjustments should be considered when refining a product design. verification of inductor-dcr current-sense pole-zero matching recall that if the inductor dcr is used as the phase current sense-element, it is necessary to select the capacitor c n such that the current sense transfer function pole at sns, matches the zero at l . the ideal response to a load step, with dc loadline (i.e., ?droop?) enab led, is shown in figure 26. figure 27 shows the load step transient response when c n is too large. v core droop response (rising or falling) lags in settling to its final value. figure 28 shows the load step re sponse when cn is too small. v core response is underdamped, an d overshoots before settling to its final voltage. once the regulator design is complete, the measured load step response can be compared to figures 26 through 28. c n should be adjusted if necessary to obta in the behavior of figure 26. current sense sensitivity error the current sense, imon, and dc loadline (droop) network component values should be designed according to the instructions in ?current sense circuit adjustments? on page 28. this will ensure the correct ratio of v imon to i droop (which determines r ll ) for the chosen system design parameters, for which no adjustment should be re quired. however, testing of the resulting circuit may reveal a measurement sensitivity error factor, which should effect v imon and i droop equally. this error may be seen as a too-large r ll value (droop voltage per load current), and as a too-large imon voltage for a given load current. a single component modification will correct both errors. the current sense resistance value per phase (either a discrete sense resistor, or the inductor dcr) is typically very small, on the order of 1m . the solder connections used in the assembly of such sense elements may contribu te significant resistance to these sense elements, resulting in a larger load-dependent voltage drop than due to the sense element alone. thus, the sensed output current value will be greater than intended for a given load current. if this is the case, then the value of ri (the isumn pin resistor) should be in creased by the factor of the sensitivity error. for example, if the current sense value is 3% larger than intended, then ri should be increased by 3%. changing ri will change the sensitivity, with respect to i out , of v imon and i droop by the same factor, thus simultaneously correcting the imon voltage e rror and the loadline resistance, while preserving the intended ratio between the two parameters. note that the assembly procedure for installing the current sense elements (sense resistors or inductors) can have a significant impact on the effective total resistance of each sense element. it is important that any adjustments to ri be performed on circuits that have been assembled with th e same procedures that will be used in mass production. the cu rrent measurement sensitivity error should be determined on a sufficient number of samples to avoid adjusting sensitivity to correct what may be a component-tolerance outlier. current sense offset error nonlinearity of the r sum resistors can induce a small positive offset in the isump voltage, and thus in the imon pin current (viewed as a positive offset in th e icc register value), and also in the droop current (viewed as an ou tput voltage negative offset). the offset error occurs as follows: for each inductor, the instantaneous voltage across its r sum resistor is approximately v rsum = v phase ? v vout . during that phase?s on time, v phase =v vin , giving v rsum-on = v vin ? v vout . during the off time, v phase = 0v, and so v rsum-off = ?v vout . for the example of v vout = 1.8v and v vin = 12v, v rsum-on = 10.2v and v rsum-off = ?1.8v, a sign-dependent magnitude difference exceeding 8v. inexpensive thick film resistors can have a voltage nonlinearity of 25ppm/volt or mo re, with the device resistance decreasing with increasing voltage. because of this r sum resistor nonlinearity, each r sum ?s (positive) current into the common isump node (during its on-time) will be biased slightly greater than the nominal v/r value expected. each r sum ?s (negative) current (during its off-time) will also be biased negatively due to the resistor nonlinearity, but less so because the r sum voltage magnitude is always much less du ring the off-time than during the on-time. this nonlinearity-b ias-current polarity mismatch causes a small positive offset error in v isump . figure 26. desired load tr ansient response waveforms o i v o figure 27. load transient response when c n is too large o i v o figure 28. load transient response when c n is too small o i v o
ISL95820 29 fn8318.0 february 4, 2013 the exact magnitude of this offset error is difficult to predict. it depends on an attribute of the sens e resistors that is typically not specified or controlled, and so not reliably quantified. it also varies with the input voltage and the output voltage. if battery powered, the input voltage can vary significantly. the output voltage is subject to the vid setting, and to a lesser extent on the droop voltage. a further complica tion is that the nonlinearity offset changes with the number of active phases. for a 4-phase configuration in ps0, four r sum resistors are subjected to the high difference in on-time compared to off-time voltage magnitudes. but in ps1, two phases are disabled with the respective phase nodes approximately following the output. so v rsum for the disabled phases is approximately zero for the entire switching cycle, reducing the offset error by half. in ps2, three phases are disabled, leaving only a fourth of the ps0 offset error. the most direct solution to the phenomenon of current sense offset due to resistor nonlinearity is to use highly linear summing resistors, such as thin film resistors. but the magnitude of the offset error typically does not warrant the considerably greater expense of doing so. instead, a correcting fixed offset can be introduced to the current sense network. for the example case described, with each thick film r sum =3.65k ? , and an i cc(max) setting of 100a, the current sense offset error in ps0 typically represents less than 1% of full scale, and is always positive. it has been found empirically that a 10m ? pulldown resistor, from the isump node to ground, provides a good correcting offset compromise, slightly under-correcting in ps0, and slight ly over-correcting in ps2, but meeting processor vendor specification tolerances with adequate margin in all cases. for other applications, a suitable compromise pull-down resistor can be determined empirically by testing over the full range of ex pected operating conditions and power states. it is recommended that this resistor be included in any vr design layout to allow population of the pull-down resistor if required. because of the high value of resistance, two smaller valued resistors in series may be preferred, to reduce the environmental sensitivity of high resistance value devices. phase current balancing phase current imbalance should be measured on a functioning circuit. first determine the co rrect assembly of the current balancing mechanism by measuring, on a stable operating regulator, the voltage difference between the isen1 pin and the remaining isen n pins (of all the operational phases) with various static loads applied. whether using the simplest circuit of figure 1 on page 1, or the pcb trace resistance compensating circuit of figure 2 on page 7, the voltage difference between any pair of the isen n pins should be very small, usually less than 1mv. if not, there may be an assembly error. then, again with various static loads applied, measure the voltage directly across each active sense element (sense resistor or inductor). any discrepancy in the phase sense element voltages beyond what can be attributed to the sense element resistance tolerance must be due to pcb trace resistance deviations. install the cross-coupli ng resistors of figure 29, and again compare the sense element voltages. now the sense element voltages should be the same among the phases in all cases (to within the tolerance of the cross-coupling resistors), and the phase current balance will be within the parametric tolerance of the sense element resistance, independently of the pcb trace resistance differences. the decision to populate the cross-coupling phase sense resistors will depend upon the magnitude of, and system tolerance of, the uncorrected imbalance current. load step ring back figure 29 shows the output volt age ring back problem during load transient response with dc loadline (i.e., ?droop?) enabled. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first order system fashion due to the nature of current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore it pulls v o back to the level dictated by i l , causing the ring back problem. this phenomenon is not observed when the output capacitor bank has very low esr and esl, such as if using only ceramic capacitors. figure 30 shows two optional circ uits for reduction of the ring back. c n is the capacitor used to match the inductor time constant. it often takes the paralleling of multiple capacitors to get the desired value. figure 30 shows that two capacitors c n.1 and c n.2 are in parallel. resistor r n is an optional co mponent to reduce the v o ring back. at steady state, c n.1 + c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective figure 29. output voltage ring back problem o i v o l i ring back figure 30. optional circuits for ring back reduction cn.2 rntcs rntc rp ri isump isumn rip cip optional vcn cn.1 rn optional
ISL95820 30 fn8318.0 february 4, 2013 capacitance is less because r n increases the impedance of the c n.1 branch. as figure 28 shows, v o tends to dip when c n is too small, and this effect will reduce the v o ring back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. r n value usually is a few ohms. c n.1 , c n.2 and r n values should be determined through tuning th e load transient response waveforms directly on the ta rget system circuit board. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i out change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i out rather than i l , and v o will not ring back. the recommended value for r ip is 100 ? . c ip should be determined by observing the load transient response waveforms in a physical circuit. the recommended range for c ip is 100pf~2000pf. however, it should be noted that the r ip -c ip branch may distort the i droop waveform. instead of being triangular as the real inductor current, i droop may have sharp spikes, which may adversely affect i droop average value detection and therefore may affect ocp accuracy. voltage regulation compensator intersil provides a microsoft excel-based spreadsheet to help design the compensator and the current sensing network, so the vr achieves constant output impedance as a stable system. please go to www.intersil.com/design/ to request spreadsheet. a vr with active droop function is a dual-loop system consisting of a voltage loop and a droop loop, which is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. figure 31 conceptually shows t1(s) measurement set-up and figure 32 conceptually shows t2(s) measurement set-up. the vr senses the inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed output voltage and feeds it to the compensator. t(1) is measured after the summing node, and t2(s) is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can be actually measured on an ISL95820 regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s) and has more meaning of system stability. t2(s) is the voltage loop gain with closed droop loop. it has more meaning of output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope. fb2 function the fb2 function allows modification of the compensator when operating in 1-phase. figure 33 shows the fb2 function. a switch (called fb2 switch) turns on (closes) to short, internally, the fb and the fb2 pins when the controller is in 4-phase, 3-phase or 2-phase mode. when fb2 is closed, capacitors c3.1 and c3.2 are in parallel, serving as part of the compensator. when the controller enters 1-phase mode, the fb2 switch opens, removing figure 31. loop gain t1(s) measurement set-up q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer figure 32. loop gain t2(s) measurement set-up q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain= channel b channel a network analyzer r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen controller in 4/3/2-phase mode controller in 1-phase mode figure 33. fb2 function
ISL95820 31 fn8318.0 february 4, 2013 c3.2 and leaving only c3.1 in the compensator. the compensator gain will increase with the removal of c3.2. by properly sizing c3.1 and c3.2, the compensator can be optimized separately for 4-, 3-, 2-phase modes and for 1-phase mode. while the fb2 switch is open and c3.2 is disconnected from the fb pin, the controller actively drives the fb2 pin voltage to track the fb pin voltage, such that th e c3.2 voltage remains equal to the c3.1 voltage. when the contro ller closes the fb2 switch, c3.2 will be reconnected to the compensator smoothly with no capacitor voltage discontinuities. the fb2 function ensures excellent transient response in 4-, 3-, 2-phase modes and in 1-phase mode. if one decides not to use the fb2 function, simply populate c3.1 only. fb3 function the fb3 function allows for chan ging the compensator loop gain depending on whether the v out droop function is enabled. figure 34 shows the fb3 pin function. a switch (called the fb3 switch) turns on to short ( internally) the fb and the fb3 pins, whenever th e droop function is enabled. resistors r1 and r1? are in pa rallel when droop is enabled, together setting the droop loadline resistance, and serving as part of the compensator. when droop is disabled, the fb3 switch turns off (opens), removing r1? and leaving only r1 in the compensator. the compensator gain will decrease with the removal of r1?. by properly sizing r1 and r1?, th e compensator can be optimized separately for both droo p enabled and disabled. to use the fb3 function , the droop resistor (r droop in equation 56) is the parallel co mbination of r1 and r1?. the compensator will use r1 only while droop is disabled, and r1 in parallel with r1? when droop is enabled. if one decides not to use the fb3 function, simply populate r1 only. start-up timing with the controller's v dd voltage above the por threshold, the start-up sequence begins when vr_on exceeds the logic high threshold. figure 35 shows the typical start-up timing. the controller uses digita l soft-start to ramp-up dac to the voltage programmed by the setvid comman d. pgood is asserted high and alert# is asserted low at the end of the ramp up. similar behavior occurs if vr_on is tied to v dd , with the soft-start sequence starting 2.3ms after v dd crosses the por threshold. voltage regulation after the start sequence, the co ntroller regulates the output voltage to the value set by the vid information per table 5. the controller will control the no-load ou tput voltage to an accuracy of 0.5% over the vid range. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. this mechanism is illustrated in figure 22. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity gain diff erential amplifier senses the vss sense voltage and adds it to the dac output. note how the illustrated dc loadline mechanism (the ?droop? mechanism, described in ?programming the dc loadline? on page 24), introduces a load-dependent reduction in the output voltage, (denoted vcc sense ), below the vid value output by the dac. the error amplifier regulates the inverting and the non-inverting input voltages to be equal, as shown in equation 55: rewriting equation 55 and subs titution of equation 5 gives equation 56: equation 56 is the exact equation required for load line implementation. the vcc sense and vss sense signals come from the processor die. the feedback will be open circuit in the absence of the processor. as figure 22 shows, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and add another ?catch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ? ~100 ? , will provide voltage feedback if the system is powered up without a processor installed. the maximum vid (output voltage command) value supported is 2.3v. any vid command (or sum of vid command and vid offset) above 2.3v will be ignored. figure 34. fb3 function r1 e/a r3 c2 c1 vref r2 c3.1 fb comp vsen controller wi th droop enabled controller wi th droop disabled fb3 r1' r1 e/a r3 c2 c1 vref r2 c3.1 fb comp vsen fb3 r1' table 5. vid table vid hex v o (v) 765 43210 vr12.5 0 0 0 0 0 0 0 0 0 0 0.00000 0 0 0 0 0 0 0 1 0 1 0.50000 0 0 0 0 0 0 1 0 0 2 0.51000 0 0 0 0 0 0 1 1 0 3 0.52000 vdd vr_on dac 2.3ms 2.5mv/s vid slew rate vid command voltage pgood alert# ?... figure 35. vr soft-start waveforms vcc sense v + droop v dac vss sense + = (eq. 55) vcc sense vss sense ? v dac r droop i droop ? = (eq. 56)
ISL95820 32 fn8318.0 february 4, 2013 0 0 0 0 0 1 0 0 0 4 0.53000 0 0 0 0 0 1 0 1 0 5 0.54000 0 0 0 0 0 1 1 0 0 6 0.55000 0 0 0 0 0 1 1 1 0 7 0.56000 0 0 0 0 1 0 0 0 0 8 0.57000 0 0 0 0 1 0 0 1 0 9 0.58000 0 0 0 0 1 0 1 0 0 a 0.59000 0 0 0 0 1 0 1 1 0 b 0.60000 0 0 0 0 1 1 0 0 0 c 0.61000 0 0 0 0 1 1 0 1 0 d 0.62000 0 0 0 0 1 1 1 0 0 e 0.63000 0 0 0 0 1 1 1 1 0 f 0.64000 0 0 0 1 0 0 0 0 1 0 0.65000 0 0 0 1 0 0 0 1 1 1 0.66000 0 0 0 1 0 0 1 0 1 2 0.67000 0 0 0 1 0 0 1 1 1 3 0.68000 0 0 0 1 0 1 0 0 1 4 0.69000 0 0 0 1 0 1 0 1 1 5 0.70000 0 0 0 1 0 1 1 0 1 6 0.71000 0 0 0 1 0 1 1 1 1 7 0.72000 0 0 0 1 1 0 0 0 1 8 0.73000 0 0 0 1 1 0 0 1 1 9 0.74000 0 0 0 1 1 0 1 0 1 a 0.75000 0 0 0 1 1 0 1 1 1 b 0.76000 0 0 0 1 1 1 0 0 1 c 0.77000 0 0 0 1 1 1 0 1 1 d 0.78000 0 0 0 1 1 1 1 0 1 e 0.79000 0 0 0 1 1 1 1 1 1 f 0.80000 0 0 1 0 0 0 0 0 2 0 0.81000 0 0 1 0 0 0 0 1 2 1 0.82000 0 0 1 0 0 0 1 0 2 2 0.83000 0 0 1 0 0 0 1 1 2 3 0.84000 0 0 1 0 0 1 0 0 2 4 0.85000 0 0 1 0 0 1 0 1 2 5 0.86000 0 0 1 0 0 1 1 0 2 6 0.87000 0 0 1 0 0 1 1 1 2 7 0.88000 0 0 1 0 1 0 0 0 2 8 0.89000 0 0 1 0 1 0 0 1 2 9 0.90000 0 0 1 0 1 0 1 0 2 a 0.91000 0 0 1 0 1 0 1 1 2 b 0.92000 0 0 1 0 1 1 0 0 2 c 0.93000 0 0 1 0 1 1 0 1 2 d 0.94000 table 5. vid table (continued) vid hex v o (v) 765 43210 vr12.5 0 0 1 0 1 1 1 0 2 e 0.95000 0 0 1 0 1 1 1 1 2 f 0.96000 0 0 1 1 0 0 0 0 3 0 0.97000 0 0 1 1 0 0 0 1 3 1 0.98000 0 0 1 1 0 0 1 0 3 2 0.99000 0 0 1 1 0 0 1 1 3 3 1.00000 0 0 1 1 0 1 0 0 3 4 1.01000 0 0 1 1 0 1 0 1 3 5 1.02000 0 0 1 1 0 1 1 0 3 6 1.03000 0 0 1 1 0 1 1 1 3 7 1.04000 0 0 1 1 1 0 0 0 3 8 1.05000 0 0 1 1 1 0 0 1 3 9 1.06000 0 0 1 1 1 0 1 0 3 a 1.07000 0 0 1 1 1 0 1 1 3 b 1.08000 0 0 1 1 1 1 0 0 3 c 1.09000 0 0 1 1 1 1 0 1 3 d 1.10000 0 0 1 1 1 1 1 0 3 e 1.11000 0 0 1 1 1 1 1 1 3 f 1.12000 0 1 0 0 0 0 0 0 4 0 1.13000 0 1 0 0 0 0 0 1 4 1 1.14000 0 1 0 0 0 0 1 0 4 2 1.15000 0 1 0 0 0 0 1 1 4 3 1.16000 0 1 0 0 0 1 0 0 4 4 1.17000 0 1 0 0 0 1 0 1 4 5 1.18000 0 1 0 0 0 1 1 0 4 6 1.19000 0 1 0 0 0 1 1 1 4 7 1.20000 0 1 0 0 1 0 0 0 4 8 1.21000 0 1 0 0 1 0 0 1 4 9 1.22000 0 1 0 0 1 0 1 0 4 a 1.23000 0 1 0 0 1 0 1 1 4 b 1.24000 0 1 0 0 1 1 0 0 4 c 1.25000 0 1 0 0 1 1 0 1 4 d 1.26000 0 1 0 0 1 1 1 0 4 e 1.27000 0 1 0 0 1 1 1 1 4 f 1.28000 0 1 0 1 0 0 0 0 5 0 1.29000 0 1 0 1 0 0 0 1 5 1 1.30000 0 1 0 1 0 0 1 0 5 2 1.31000 0 1 0 1 0 0 1 1 5 3 1.32000 0 1 0 1 0 1 0 0 5 4 1.33000 0 1 0 1 0 1 0 1 5 5 1.34000 0 1 0 1 0 1 1 0 5 6 1.35000 0 1 0 1 0 1 1 1 5 7 1.36000 table 5. vid table (continued) vid hex v o (v) 765 43210 vr12.5
ISL95820 33 fn8318.0 february 4, 2013 0 1 0 1 1 0 0 0 5 8 1.37000 0 1 0 1 1 0 0 1 5 9 1.38000 0 1 0 1 1 0 1 0 5 a 1.39000 0 1 0 1 1 0 1 1 5 b 1.40000 0 1 0 1 1 1 0 0 5 c 1.41000 0 1 0 1 1 1 0 1 5 d 1.42000 0 1 0 1 1 1 1 0 5 e 1.43000 0 1 0 1 1 1 1 1 5 f 1.44000 0 1 1 0 0 0 0 0 6 0 1.45000 0 1 1 0 0 0 0 1 6 1 1.46000 0 1 1 0 0 0 1 0 6 2 1.47000 0 1 1 0 0 0 1 1 6 3 1.48000 0 1 1 0 0 1 0 0 6 4 1.49000 0 1 1 0 0 1 0 1 6 5 1.50000 0 1 1 0 0 1 1 0 6 6 1.51000 0 1 1 0 0 1 1 1 6 7 1.52000 0 1 1 0 1 0 0 0 6 8 1.53000 0 1 1 0 1 0 0 1 6 9 1.54000 0 1 1 0 1 0 1 0 6 a 1.55000 0 1 1 0 1 0 1 1 6 b 1.56000 0 1 1 0 1 1 0 0 6 c 1.57000 0 1 1 0 1 1 0 1 6 d 1.58000 0 1 1 0 1 1 1 0 6 e 1.59000 0 1 1 0 1 1 1 1 6 f 1.60000 0 1 1 1 0 0 0 0 7 0 1.61000 0 1 1 1 0 0 0 1 7 1 1.62000 0 1 1 1 0 0 1 0 7 2 1.63000 0 1 1 1 0 0 1 1 7 3 1.64000 0 1 1 1 0 1 0 0 7 4 1.65000 0 1 1 1 0 1 0 1 7 5 1.66000 0 1 1 1 0 1 1 0 7 6 1.67000 0 1 1 1 0 1 1 1 7 7 1.68000 0 1 1 1 1 0 0 0 7 8 1.69000 0 1 1 1 1 0 0 1 7 9 1.70000 0 1 1 1 1 0 1 0 7 a 1.71000 0 1 1 1 1 0 1 1 7 b 1.72000 0 1 1 1 1 1 0 0 7 c 1.73000 0 1 1 1 1 1 0 1 7 d 1.74000 0 1 1 1 1 1 1 0 7 e 1.75000 0 1 1 1 1 1 1 1 7 f 1.76000 1 0 0 0 0 0 0 0 8 0 1.77000 1 0 0 0 0 0 0 1 8 1 1.78000 table 5. vid table (continued) vid hex v o (v) 765 43210 vr12.5 1 0 0 0 0 0 1 0 8 2 1.79000 1 0 0 0 0 0 1 1 8 3 1.80000 1 0 0 0 0 1 0 0 8 4 1.81000 1 0 0 0 0 1 0 1 8 5 1.82000 1 0 0 0 0 1 1 0 8 6 1.83000 1 0 0 0 0 1 1 1 8 7 1.84000 1 0 0 0 1 0 0 0 8 8 1.85000 1 0 0 0 1 0 0 1 8 9 1.86000 1 0 0 0 1 0 1 0 8 a 1.87000 1 0 0 0 1 0 1 1 8 b 1.88000 1 0 0 0 1 1 0 0 8 c 1.89000 1 0 0 0 1 1 0 1 8 d 1.90000 1 0 0 0 1 1 1 0 8 e 1.91000 1 0 0 0 1 1 1 1 8 f 1.92000 1 0 0 1 0 0 0 0 9 0 1.93000 1 0 0 1 0 0 0 1 9 1 1.94000 1 0 0 1 0 0 1 0 9 2 1.95000 1 0 0 1 0 0 1 1 9 3 1.96000 1 0 0 1 0 1 0 0 9 4 1.97000 1 0 0 1 0 1 0 1 9 5 1.98000 1 0 0 1 0 1 1 0 9 6 1.99000 1 0 0 1 0 1 1 1 9 7 2.00000 1 0 0 1 1 0 0 0 9 8 2.01000 1 0 0 1 1 0 0 1 9 9 2.02000 1 0 0 1 1 0 1 0 9 a 2.03000 1 0 0 1 1 0 1 1 9 b 2.04000 1 0 0 1 1 1 0 0 9 c 2.05000 1 0 0 1 1 1 0 1 9 d 2.06000 1 0 0 1 1 1 1 0 9 e 2.07000 1 0 0 1 1 1 1 1 9 f 2.08000 1 0 1 0 0 0 0 0 a 0 2.09000 1 0 1 0 0 0 0 1 a 1 2.10000 1 0 1 0 0 0 1 0 a 2 2.11000 1 0 1 0 0 0 1 1 a 3 2.12000 1 0 1 0 0 1 0 0 a 4 2.13000 1 0 1 0 0 1 0 1 a 5 2.14000 1 0 1 0 0 1 1 0 a 6 2.15000 1 0 1 0 0 1 1 1 a 7 2.16000 1 0 1 0 1 0 0 0 a 8 2.17000 1 0 1 0 1 0 0 1 a 9 2.18000 1 0 1 0 1 0 1 0 a a 2.19000 1 0 1 0 1 0 1 1 a b 2.20000 table 5. vid table (continued) vid hex v o (v) 765 43210 vr12.5
ISL95820 34 fn8318.0 february 4, 2013 dynamic vid operation the controller receives vid commands via either the serial vid (svid) port or the serial i 2 c/smbus/pmbus port. it responds to vid changes by slewing to the new voltage at a slew rate indicated in the setvid command. there are three setvid slew rates: setvid_fast, setvid_slow, and setvid_decay. setvid_fast command prompts the controller to enter ccm and to actively drive the output voltage to the new vid value at a slew rate up to but not to exceed 10mv/s. setvid_slow command prompts th e controller to enter ccm and to actively drive the output voltage to the new vid value at a slew rate up to but not to exceed 2.5mv/s. setvid_decay command prompts the controller to enter dem. the output voltage will decay down to the new vid value at a slew rate determined by the load. if the vo ltage decay rate is too fast, the controller will limit the voltage slew rate to the fast slew rate of 10mv/s. if dem is disabled by the prog2 programming resistor, the svid command "setvid_decay" executes as single-phase (phase 1 only) ?setvid_slow? except that alert# signaling mimics that of the ?setvid_decay? command. alert# is asserted (low) upon completion of all non-zero vid transitions. figure 36 shows setvid deca y pre-emptive response, which occurs whenever a new vid command is received before completion of a previous setvid decay command. in the example scenario of figure 36, the controller receives a setvid_decay command at t1. the vr enters dem and the output voltage vo decays down slowly. at t2, before vo reaches the intended vid target of the setvid_decay command, the controller receives a setvid_fas t (or setvid_slow) command to go to a voltage higher than the actual vo. the controller will preempt the decay to the lower voltage and slew vo to the new target voltage at the slew rate specified by the setvid command. at t3, vo reaches the new target voltage and the controller asserts the alert# signal. slew rate compensation circuit for vid transition during a large vid tran sition, the dac steps through the vid table at proscribed step rate. for example, the dac may change 1 tick (10mv) per 1 + s, controlling output voltage v core slew rate at less than 10mv/s, or 1 tick per 4 + s, controlling output voltage v core slew rate at less than 2.5mv/s. figure 37 shows the waveforms of vid transition. during vid transition, the output capacitor is being charged and discharged, causing c out x dv core /dt current on the inductor. the controller senses the inductor current increase during the up transition (as the i droop_vid waveform shows) and will droop the output voltage v core accordingly, making v core slew rate slow. similar behavior occurs during the down transition. to get the correct v core slew rate during vid transition, one can add the r vid -c vid branch, whose current i vid compensates for i droop_vid . 1 0 1 0 1 1 0 0 a c 2.21000 1 0 1 0 1 1 0 1 a d 2.22000 1 0 1 0 1 1 1 0 a e 2.23000 1 0 1 0 1 1 1 1 a f 2.24000 1 0 1 1 0 0 0 0 b 0 2.25000 1 0 1 1 0 0 0 1 b 1 2.26000 1 0 1 1 0 0 1 0 b 2 2.27000 1 0 1 1 0 0 1 1 b 3 2.28000 1 0 1 1 0 1 0 0 b 4 2.29000 1 0 1 1 0 1 0 1 b 5 2.30000 table 5. vid table (continued) vid hex v o (v) 765 43210 vr12.5 figure 36. setvid decay pre-emptive behavior vo setv id_decay s etv id_fast/slow t_alert vid alert# t1 t2 t3 figure 37. slew rate compensation circuit for vid transition x 1 e/a dac vid r droop i droop_vid vdac fb comp vcore vss sense vids rtn vss internal to ic rvid cvid vid vfb vcore ivid idroop_vid ivid optional
ISL95820 35 fn8318.0 february 4, 2013 choose the r, c values from the reference design as a starting point, then tweak the actual values on the board to get the best performance. during normal transient response, the fb pin voltage is held constant, therefore is virtual grou nd in small signal sense. the r vid - c vid network is between the virtual ground and the real ground, and hence has no effect on transient response. extended v out range if a higher (than max supported vi d) output voltage is required, such as for overclocking applic ations, the feedback voltage can be divided down to the fb pin such that v fb = vid for v vout > vid. figure 38 shows the addition of resistor rg (and optional 2n7002 switch), which adds the feedback voltage division to the schematic of figure 22 on page 25. with the 2n7002 off, v vout = vid ? vdroop = vid ? rdroop*idroop, the same as in the normal conf iguration. but with the 2n7002 switch closed, v out = vid -(idroop - vid/rg)*rdroop = vid (1 + rdroop/rg) ? idroop*rdroop. the unloaded output voltage is then v vout (unloaded) = vid (1 + rdroop/rg), and the droop vo ltage vdroop = idroop*rdroop. notice that the droop voltage is determined by the droop resistor, and is independent of whether the feedback voltage is divided or not. then rg is selected to obtain the desired divider ratio. the programmed loadline resistance is not affected by the addition of rg . ? to avoid false ovp faults, the ovp threshold may have to be changed to 3.3v fixed, rather than at the relative value of 300mv above vid, via the pmbus interface (see ?fault protection? on page 35 for details). the ovp thresh old must be changed prior to turning on the en_ext_vout switch. because of ovp, a practical upper limit for v vout is 3.04v, which is also the maximum defined vid value. the maximum supported vid value in the ISL95820 is 2.3v, so the inverse divider ratio (1 + rdroop/rg) should not exceed 1.32. because the higher output voltage requires a higher switching duty cycle, a higher slope compensation value may be required for stability. the abrupt inclusion of rg to the feedback network will create a step in the selected output voltage, which may result in high overshoot or ringing in the output. the rc network on the gate of the 2n7002 may slow the transiti on from normal range to extended range. note that with extended range enabled, the vid step size will increase by the inverse divider ratio. consequently, the dvid slew rates will also increase by the same ratio. fault protection the ISL95820 provides overcurrent, current-balance and overvoltage fault protections. the controller also provides over-temperature protection. the controller determines overcurrent protection (ocp) by comparing the average value of the droop current i droop with an internal current source threshold as table 4 shows. it declares ocp when i droop is above the threshold for 120s. the controller monitors the isen pin voltages to determine current-balance protection. if the difference of one isen pin voltage and the average isens pin voltage is greater than 9mv (for at most 4ms), the controller w ill declare a fault and latch off. the controller takes the same actions for all of the above fault protections: de-assertion of pg ood and turn-off of all the high-side and low-side power mosfets. any residual inductor current will decay through the mosfet body diodes. the controller will declare an over voltage protection (ovp) fault and de-assert pgood if the voltage of the isumn pin (approximately the output voltage) exceeds the vid set value by +300mv. optionally, the overvoltage threshold can be set, via the pmbus interface, to 3.3v fixed. the controller will immediately declare an ov fault, de-assert pgood, and turn on the low-side power mosfets. the low-side power mosfets remain on until the output voltage is pulled down below the vid set value when all power mosfets are turned off. if the output voltage rises above the vid set value again, the protection process is repeat ed. this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. the default overvoltage fault threshold is 2.6v when output voltage ramps up from 0v. the overvoltage fault threshold reverts to vid + 300mv after the output voltage settles. optionally, via the pmbus interface, the overvoltage threshold can be fixed at 3.3v prior to increasing vid from 0v. all the above fault conditions can be reset by bringing vr_on low or by bringing v dd below the por threshold. when vr_on and v dd return to their high operating levels, a soft-start will occur. figure 38. extending the range of vout with a feedback resistor divider x 1 e/a dac vid rdroop idroop vdac vdroop fb comp vcc sense = vout vss sense rtn vss internal to ic rg 2n7002 en_ext_vout comp
ISL95820 36 fn8318.0 february 4, 2013 table 6 summarizes the fault protections. vr_hot#/alert# behavior the controller drives 60a current source out of the ntc pin. the current source flows through the respective ntc resistor networks on the pins and creates voltages that are monitored by the controller through an a/d co nverter (adc) to generate the tzone value. table 7 shows the programming table for tzone. the user needs to scale the ntc network resistance, such that it generates the ntc pin voltage that corresponds to the left-most column. do not use any capacitor to filter the voltage. figure 39 shows how the ntc networ k should be designed to get correct vr_hot#/alert# behavior when the system temperature rises and falls, manifested as the ntc pin voltage falls and rises. the series of events are: 1. the temperature rises so the ntc pin voltage drops. tzone value changes accordingly. 2. the temperature crosses the threshold where tzone register bit 6 changes from 0 to 1. 3. the controller changes status_1 register bit 1 from 0 to 1. 4. the controller asserts alert#. 5. the cpu reads status_1 register value to know that the alert assertion is due to tzone register bit 6 flipping. 6. the controller clears alert#. 7. the temperature continues rising. 8. the temperature crosses the threshold where tzone register bit 7 changes from 0 to 1. 9. the controller asserts vr_h ot# signal. the cpu reduces power consumption, and the sy stem temperature eventually drops. 10. the temperature crosses the threshold where tzone register bit 6 changes from 1 to 0. this threshold is 1 adc step lower than the one when vr_hot# gets asserted, to provide 3% hysteresis. 11. the controllers de-asserts vr_hot# signal. 12. the temperature crosses the threshold where tzone register bit 5 changes from 1 to 0. this threshold is 1 adc step lower than the one when alert# gets asserted during the temperature rise to provide 3% hysteresis. 13. the controller changes status_1 register bit 1 from 1 to 0. 14. the controller asserts alert#. 15. the cpu reads status_1 register value to know that the alert assertion is due to tzone register bit 5 flipping. 16. the controller clears alert#. to disable the ntc function, connect the ntc pin to vdd using a pullup resistor. serial interfaces serial vid (svid) supported data and configuration registers the controller supports the fo llowing data and configuration registers, accessible via the svid interface. the device is compliant with intel vr12.5/vr12/imvp7 svid protocol. to ensure proper cpu op eration, refer to this document for svid bus design and layout guidelines; each platform requires table 6. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm4/phase tri- state, pgood latched low vr_on toggle or vdd toggle phase current imbalance 4ms overvoltage: v out > vid + 300mv (optionally 3.3v fixed) immediate pgood latched low. actively pulls the output voltage to below vid value, then tri-states the phase switches (phases 1, 2, 3) and pwm4. overvoltage: v out > 2.6v = vidmax + 300mv (optionally 3.3v fixed) during output voltage ramp up from 0v table 7. tzone table vntc (v) tmax (%) tzone 0.84 >100 ffh 0.88 100 ffh 0.92 97 7fh 0.96 94 3fh 1.00 91 1fh 1 bit 6 =1 bit 7 =1 bit 5 =1 temp zone register 0001 1111 0011 1111 0 1 11 1111 1 111 1111 0 1 11 1111 0011 1111 0001 1111 status 1 register = ?001? = ?0 1 1? = ?0 0 1? temp zone 7 2 3 5 svid alert# vr_hot# 4 gerreg status1 8 6 9 10 11 1111 1111 0111 1111 0011 1111 0001 1111 12 13 15 gerreg status1 14 16 3% hysteresis vr temperature figure 39. vr_hot#/alert# behavior 1.04 88 0fh 1.08 85 07h 1.12 82 03h 1.16 79 01h 1.2 76 01h >1.2 <76 00h table 7. tzone table vntc (v) tmax (%) tzone
ISL95820 37 fn8318.0 february 4, 2013 different pull-up impedance on the svid bus, while impedance matching and spacing among data, clk, and alert# signals must be followed. common mistakes are insufficient spacing among signals and improper pull-up impedance. the svid alertb is asserted for the following conditions: 1. when vrsettled is asserted for non-zero volt commandedvid. if the comman dedvid is changed, the alertb will de-assert while the dac is moving to the new target. 2. therm alert changing from 0 to 1 or from 1 to 0. (read status1 required to clear this alert flag.) 3. i cc(max) alert changing from 0 to 1 or from 1 to 0. (read status1 required to clear this alert flag.) serial pmbus (i 2 c/smbus/pmbus) supported data and configuration registers the ISL95820 features smbus, pmbus, and i 2 c with fixed write address 80h and fixed read addre ss 81h. (the least significant bit of the 8-bit address is for write (0h) and read (1h).) smbus/pmbus includes an alert# line and packet error check (pec) to ensure data properly tran smitted. in addition, the output voltage and offset, droop enable, overvoltage setpoint, and the priority of svid and smbus/pmbus/i 2 c can be written and read via this bus, as summarized in table 9. output current and voltage setting can be read as summarized in table 10. for proper operation, users should follow the smbus, pmbus, and i 2 c protocol, as shown in figure 42. note that stop (p) bit is not allowed before the repeated start condition when ?reading? contents of register, as shown in figure 42. table 8. supported data and configuration registers index register name description default value 00h vendor id uniquely identifies the vr vendor. assigned by intel. 12h 01h product id uniquely identifies the vr product. intersil assigns this number. 10h 02h product revision uniquely identifies the revision of the vr control ic. intersil assigns this data. 05h protocol id identifies what revision of svid protocol the controller supports. 03h 06h capability identifies the svid vr capabilities and which of the optional telemetry registers are supported. 81h 10h status_1 data register read after alert# signal. indicating if a vr rail has settled, has reached vrhot condition or has reached icc max. 00h 11h status_2 data register showing status_2 communication. 00h 12h temperature zone data register showing temperature zones that have been entered. 00h 15h icc read output current, range 00h to ffh 1ch status_2_ lastread this register contains a copy of the status_2 data that was last read with the getreg (status_2) command. 00h 21h i cc(max) data register containing the icc max the platform supports, set at start-up by resistors rprog1 and rprog2. the platform design engineer programs this value during the design process. binary format in amps, i.e., 100a = 64h refer to table 2 22h temp max not supported 00h 24h sr-fast slew rate normal. the fastest slew rate the platform vr can sustain. binary format in mv/s. i.e., 0ah = 10mv/s. 0ah 25h sr-slow is 4x slower than normal. binary format in mv/s. i.e., 02h = 2.5mv/s 02h 26h v boot if programmed by the platform, the vr supports v boot voltage during start-up ramp. the vr will ramp to v boot and hold at v boot until it receives a new setvid command to move to a different voltage. 00h 30h v out max this register is programmed by the master and sets the maximum vid the vr will support. if a higher vid code is received, the vr will respond with ?not supported? acknowledge. b5h 31h vid setting data register containing currently programmed vid voltage. see table 5 beginning on page 31. 32h power state register containing the current programmed power state. 00h 33h voltage offset sets offset in vid steps added to the vid setting for voltage margining , expressed as an 8-bit 2's-complement offset value. for example: ... feh = -2 vid steps ffh = -1 vid step 00h = zero offset, no margin 01h = +1 vid step 02h = +2 vid steps ... 00h 34h multi vr config data register that configures multiple vrs behavior on the same svid bus. 00h table 8. supported data and configuration registers (continued) index register name description default value
ISL95820 38 fn8318.0 february 4, 2013 smbus/pmbus/i 2 c allows programming the registers of table 9, 11ms after vcc above por, an d after vr_on input is high. figure 40. simplified smbus/pmbus/i 2 c initialization timing diagram wh en no bus write command received 5v vcc enable 9 ms 2 ms vcc por time out reader done reader re-loaded 4.6 ms indefinitely reader re-loaded 4.6 ms d0 to f3 command resistor divider to reset 0c- 0f user can change v out svid 0c-0f configuration loaded with new dc-df d0 to f3 command no succesful bus send command figure 41. simplified smbus/pmbus/ i 2 c initialization timing diagram when bus write command sucessfully received 5v vcc enable 9 ms 2 ms vcc por time out reader done indefinitely dc to df command d1 to f3 command d0 to f3 command d0 to f3 command svid 0c-0f configuration loaded with new dc-df d0 to f3 command dc to df command svid 0c-0f configuration loaded with dc-df use previous svid 0c-0f v out figure 42. smbus/pmbus/i 2 c protocol s slave address_0 1 7 + 1 command code 1 8 low data byte high data byte pec a 1 8 a 1 8 a 1 8 a 1 a 1 p write byte/word protocol example command: dah set_vid (one word, high data byte and ack are not used) optional 9 bits for smbus/pmbus not used in i 2 c s: start condition a: acknowledge (?0?) n: not acknowledge (?1?) rs: repeated start condition p: stop condition pec: packet error checking r: read (?1?) w: write (?0?) not used for one byte word acknowledge or data from slave, ISL95820 controller
ISL95820 39 fn8318.0 february 4, 2013 table 9. smbus, pmbus, and i 2 c write and read registers command code access default command name description d4h[0] r/w droop_en 0h=droop disabled; 1h = droop enabled; default determined by prog2 pin resistance to ground. see table 3. when the controller is reset by the vr_on pin transitioning from low to high, the prog2 resistance is measured and this register is stored accordingly. d6h[1:0] r/w 00h lock_svid set svid and smbus/pmbus/i 2 c priority (see table 11 for details) d8h[0] r/w 00h set_ov 0h = vid+300mv, 1h = 3.3v fixed. dah[7:0] r/w set_vid svid bus vid code. see table 5 beginning on page 31. default to v boot value on start-up, determined by prog2 pin resistance to ground. dbh[7:0] r/w 00h set_offset svid bus vid offset code, expressed as an 8-bit 2's-complement offset value. for example: ... feh = -2 vid steps ffh = -1 vid step 00h = zero offset, no margin 01h = +1 vid step 02h = +2 vid steps ... table 10. smbus, pmbus, and i 2 c telemetries code word length (byte) command name description typical resolution 8bh two read_vout output voltage (vid+offset, see table 5 8-bit, 10mv 8ch two read_iout output current (ff = i cc(max) 8-bit, i cc(max) /255
ISL95820 40 fn8318.0 february 4, 2013 table 11. lock_svid d6h svid smbus, pmbus or i 2 c final dac targeted applications setvid setps (1/2/3) and setdecay set offset setvid set offset 00h yes yes yes not not sv_vid + sv_offset not overclocking 01h yes yes yes not yes sv_vid + pm_offset not overclocking 02h yes ack only ack only not yes sv_vid + pm_offset overclocking 03h ack only ack only ack only yes yes pm_vid + pm_offset overclocking note: 8. the ISL95820 controller is designed such that all svid commands are acknowledged as if the smbus, pmbus or i 2 c does not exist. to avoid conflict between smbus/pmbus/i 2 c and svid bus during operation, execute this command prior to writing the vid setting or offset commands. with 01h option, smbus/pmbus/i 2 c?s offset should only adjust slightly higher or lower (say 20mv) than svid offset for margining purpose or pcb loss compensation so that cpu will no t draw significantly more power in psi1/2/3/decay mode. to program full range of pm_offset for overclocking applications, select 02h or 03h options. 03h option gives full control of the output voltage (vid+offset) via smbus/pmbus/i 2 c, commonly used in overclocking applications. prior to a success ful written pmbus vid or offset, the contro ller will continue executing svid vid o r offset command.
ISL95820 41 fn8318.0 february 4, 2013 layout guidelines ISL95820 pin number symbol layout guidelines bottom pad gnd connect this ground pad to the ground plane throug h low impedance path. recommend use of at least 5 vias to connec t to ground planes in pcb internal layers. this is also the primary conduction path for heat removal. 1 vr_on no special consideration. 2 pgood no special consideration. 3 imon no special consideration. 4 vr_hot# no special consideration. 5 ntc the ntc thermistor needs to be placed close to th e thermal source that is monitored to determine cpu v core thermal throttling. recommend placing it at the hottest spot of the cpu v core vr. 6 comp place the compensator components in general proximity of the controller. 7fb 8fb2 9fb3 10 isen4 each isen pin has a capacitor (cisen) decoupling it to vsumn, then through another capacitor (cvsumn) to gnd. place cisen capacitors as close as possible to the controller and keep the following loops small: 1. any isen pin to another isen pin 2. any isen pin to gnd the red traces in the following drawing show the loops that need to minimized. 11 isen3 12 isen2 13 isen1 14 rtn place the rtn filter in close proximity of the controller for good decoupling. v o isen3 l3 risen isen2 isen1 l2 l1 risen risen phase1 phase2 phase3 ro ro ro gnd cisen cisen cisen cvsumn vsumn
ISL95820 42 fn8318.0 february 4, 2013 15 isumn place the current sensing circuit in general proximity of the controller. place capacitor c n very close to the controller. place the inductor temperature sensing ntc thermistor next to phase-1 inductor (l1) so it senses the inductor temperature correctly. each phase of the power stage sends a pair of vsump and vs umn signals to the controller. run these two signals traces in parallel fashion with decent width (>20mil). important: sense the inductor current by routing the sensin g circuit to the inductor pads. route the isumpn and isenn resistor traces to the phase-side pad of each inductor. the isumnn network ro resistor traces should be routed to the vout-side pad of each inductor. if possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of th e pads. if no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. the following drawings show the two preferred ways of ro uting current sensing traces. 16 isump 17 vdd a capacitor decouples it to gnd. place it in close proximity of the controller. 18 boot1 place the phase1 bootstrap capacitor be tween boot1 and phase1, near the controller. 19 phase1 no special consideration. 20 ugate1 no special consideration. 21 lgate1 no special consideration. 22 boot2 place the phase2 bootstrap capacitor between boot2 and phase2, near the controller. 23 phase2 no special consideration. 24 ugate2 no special consideration. 25 vccp a capacitor decouples it to gnd. place it in close proximity of the controller. 26 lgate2 no special consideration. 27 lgate3 no special consideration. 28 phase3 no special consideration. 29 ugate3 no special consideration. 30 boot3 place the phase3 bootstrap capacitor between boot3 and phase3, near the controller. 31 pwm4 no special consideration. 32 vin a capacitor decouples it to gnd. place it in close proximity of the controller. 33 prog3 no special consideration. 34 prog2 no special consideration. 35 prog1 no special consideration. 36, 37, 38, 39, 40 i2data, i2clk, sda, alert#, sclk follow intel recommendation. layout guidelines (continued) ISL95820 pin number symbol layout guidelines inductor current-sensing traces vias inductor current-sensing traces
ISL95820 43 fn8318.0 february 4, 2013 typical performance figure 43. soft-start, v in ? = ? 12v, i o ? = ? 5a, vid ? = ? 1.7v, ch1: phase1, ch2: vr_on, ch3: pgood, ch4: v out figure 44. shut down, v in ? = ? 12v, i o ? = ? 5a, vid ? = ? 1.7v, ch1: phase1, ch2: vr_on, ch3: pgood, ch4: v out figure 45. steady state, ps0, v in ? = ? 12v, i o ? = ? 5a, vid ? = ? 1.8v ch1: phase1, ch2: phase2, ch3: phase3, ch4: ? v out , phase4 not shown figure 46. steady state, ps1, v in ? = ? 12v, i o ? = ? 5a, vid ? = ? 1.8v ch1: phase1, ch2: phase2, ch3: phase3, ch4: ? v out , phase4 not shown figure 47. steady state, ps2, v in ? = ? 12v, i o ? = ? 5a, vid ? = ? 1.8v ch1: phase1, ch2: phase2, ch3: phase3, ch4: ? v out , phase4 not shown
ISL95820 44 fn8318.0 february 4, 2013 figure 48. vr1 load release response, v in ? = ? 12v, vid ? = ? 1.8v, i o ? = ? 61a/1a, slew time = 50ns, ll ? = ? 1.5m , ch1: phase1, ch2: phase2 , ch3: phase3, ch4: ? v out , phase4 not shown figure 49. vr1 load insertion response, v in ? = ? 12v, vid ? = ? 1.8v, i o ? = ? 1a/61a, slew time = 50ns, ll ? = ? 1.5m , ch1: phase1, ch2: phase2 , ch3: phase3, ch4: ? v out , phase4 not shown figure 50. setvid-fast response, i o ? = ? 5a, vid ? = ? 1.6v ? - ? 1.8v, ch1: phase1, ch3: ? alert#, ch4: v out figure 51. setvid-fast response, i o ? = ? 5a, vid ? = ? 1.8v ? - ? 1.6v, ch1: phase1, ch3: ? alert#, ch4: v out figure 52. setvid-slow response, i o ? = ? 5a, vid ? = ? 1.6v ? - ? 1.8v, ch1: phase1, ch3: ? alert#, ch4: v out figure 53. setvid-slow response, i o ? = ? 5a, vid ? = ? 1.8v ? - ? 1.6v, ch1: phase1, ch3: ? alert#, ch4: v out typical performance (continued)
ISL95820 45 fn8318.0 february 4, 2013 figure 54. setvid decay response, i o ? = ? 5a, vid ? = ? 1.8v ? - ? 1.6v, ch1: phase1, ch3: ? alert#, ch4: v out figure 55. setvid slow response following setvid decay, i o ? = ? 5a, vid ? = ? 1.6v ? - ? 1.8v, ch1: phase1, ch3: ? alert#, ch4: v out figure 56. setvid fast response following setvid decay, i o ? = ? 5a, vid ? = ? 1.6v ? - ? 1.8v, ch1: phase1, ch3: ? alert#, ch4: v out typical performance (continued)
ISL95820 46 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8318.0 february 4, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL95820 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web for the latest rev. date revision change february 4, 2013 fn8318.0 initial release.
ISL95820 47 fn8318.0 february 4, 2013 package outline drawing l40.5x5 40 lead thin quad flat no-lead plastic package rev 1, 9/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.27mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (40x 0.60) 0.00 min 0.05 max (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail ?x? c c 5 6 a b b 0.10 m a c c 0.10 // 5.00 5.00 3.50 5.00 0.40 4x 3.60 36x 0.40 3.50 0.20 40x 0.4 0 .1 0.750 0.050 0.2 ref (40x 0.20) (36x 0.40 b package outline jedec reference drawing: mo-220whhe-1 7. 6 4

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